Multi-level flash memory with temperature compensation
First Claim
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1. A semiconductor memory device comprising:
- a plurality of memory cells configured to store multi-level data;
a plurality of wordlines connected to the plurality of memory cells; and
a first circuit configured to supply a temperature-dependent voltage to a selected one of the wordlines to read or verify a state of a selected memory cell, wherein the first circuit includes a first voltage generation circuit configured to supply a temperature-independent reference voltage and a second voltage generation circuit configured to supply a flexible reference voltage, the first circuit further includes a differential amplifier configured to compare the temperature-independent reference voltage with the flexible reference voltage.
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Abstract
A multi-level semiconductor memory device preferably includes a plurality of wordlines connected to memory cells configured to store multi-level data. A first circuit supplies a temperature-responsive voltage to a selected wordline in order to read a state of a selected memory cell. A second circuit supplies a predetermined voltage to non-selected wordlines. The first circuit preferably includes a semiconductor element that varies its resistance in accordance with temperature. Reliable program-verifying and reading functions are preferably provided despite migration of threshold voltage distribution profiles due to temperature variations.
211 Citations
16 Claims
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1. A semiconductor memory device comprising:
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a plurality of memory cells configured to store multi-level data;
a plurality of wordlines connected to the plurality of memory cells; and
a first circuit configured to supply a temperature-dependent voltage to a selected one of the wordlines to read or verify a state of a selected memory cell, wherein the first circuit includes a first voltage generation circuit configured to supply a temperature-independent reference voltage and a second voltage generation circuit configured to supply a flexible reference voltage, the first circuit further includes a differential amplifier configured to compare the temperature-independent reference voltage with the flexible reference voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory device comprising:
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a memory cell array comprising a plurality of memory cells, wordlines, and bitlines, said memory cells configured to store multi-level data;
a first voltage generation circuit configured to generate a temperature-independent first voltage having a predetermined level;
a second voltage generation circuit configured to generate a temperature-dependent flexible reference voltage; and
a third circuit configured to compare the temperature-independent first voltage to the flexible reference voltage, said third circuit further configured to supply a temperature-dependent output voltage to a selected one of the wordlines, said output voltage corresponding to a difference between the temperature-independent first voltage and the flexible reference voltage. - View Dependent Claims (9, 10, 11, 12)
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13. A method of operating a multi-level data state semiconductor memory device having a plurality of wordlines connected to a plurality of memory cells, said method comprising:
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selecting a wordline from among a plurality of wordlines, said selected wordline corresponding to a selected memory cell;
generating a temperature-independent fixed reference voltage and a temperature-dependent flexible reference voltage;
comparing the temperature-independent fixed reference voltage with the temperature-dependent flexible reference voltage to generate a temperature-dependent voltage;
supplying the temperature-dependent voltage to the selected wordline; and
supplying predetermined voltages to nonselected wordlines. - View Dependent Claims (14, 15, 16)
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Specification