Variable level memory

• US 6,870,767 B2
• Filed: 09/18/2003
• Issued: 03/22/2005
• Est. Priority Date: 09/18/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Fackenthal, Richard E., Rudelic, John C.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/666,988
• Publication Number:
  US 20040057355A1
• Time in Patent Office: 551 Days
• Field of Search: 365/185.03, 365/185.2, 365/185.21
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

There exists a tradeoff between the fidelity of data storage and the number of bits stored in a memory cell. The number of bits may be increased per cell when fidelity is less important. The number of bits per cell may be decreased when fidelity is more important. A memory, in some embodiments, may change between storage modes on a cell by cell basis.

Claims

1. A method comprising:

storing data at a first density in a first cell in a first memory array;

storing data at a second density in a second cell in the first memory array; and

dynamically changing the number of bits stored per cell.

2. The method of claim 1 wherein storing data at a second density in a second cell includes storing fewer bits per cell in one of said first or second cells.

3. The method of claim 1 including changing the number of bits stored per cell dynamically.

4. The method of claim 2 including storing data at levels which are spaced from one another in said cell in order to improve the read fidelity.

5. The method of claim 4 including storing data in a cell including a plurality of levels and filling less than all of said levels.

6. The method of claim 5 including storing data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

7. An article comprising a medium storing instructions, that, if executed, enable a processor-based system to:

store data at a first density in a first cell in a first memory;

store data at a second density in a second cell in said first memory array; and

dynamically change the number of bits stored per cell.

8. The article of claim 7 further storing instructions that enable the processor-based system to store fewer bits per cell in one of said first or second cells.

9. The article of claim 8 further storing instructions that able the processor-based system to store data at levels which are spaced from one another in said cell in order to improve the read fidelity.

10. The article of claim 9 further storing instructions that enable the processor-based system to store data in a cell including a plurality of levels and fill less than all of said levels.

11. The article of claim 10 further storing instructions that enable the processor-based system to store data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.

12. A memory comprising:

a memory array including a first and second cell; and

a controller coupled to said array to store data in said array at a first density in the first cell and to store data at a second density in the second cell wherein said controller to dynamically change the number of bits stored per cell.

13. The memory of claim 12 wherein said memory is a flash memory.

14. The memory of claim 13 wherein said memory is a multi-level cell memory.

15. The memory of claim 12 wherein said controller stores fewer bits per cell in one of said first or second cells.

16. The memory of claim 12 wherein said controller stores data at levels that are spaced from one another in said cell in order to improve the read fidelity.

17. The memory of claim 16 wherein said controller stores data in a cell including a plurality of levels and fills less than all of the levels.

18. The memory of claim 12 wherein said controller stores data in regularly spaced levels within a cell while leaving intervening levels within the cell unoccupied by stored data.