Bit allocation among carriers in multicarrier communications

• US 6,870,888 B1
• Filed: 11/23/1999
• Issued: 03/22/2005
• Est. Priority Date: 11/25/1998
• Status: Expired due to Term

• Current Assignee: TQ Delta LLC (Techquity Capital Management, LLC)
• Original Assignee: Aware Incorporated (Crowley Holdings Preferred LLC)
• Inventors: Shapiro, Jerome M., Sandberg, Stuart D., Tzannes, Marcos C.
• Primary Examiner(s): Liu, Shuwang
• Application Number:
  US09/600,971
• Time in Patent Office: 1,946 Days
• Field of Search: 375/260, 375/220, 375/219, 375/225, 375/227, 370/242, 370/252, 370/470, 370/471
• US Class Current: 375/260
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 5/0044 allocation of payload

Abstract

A technique is provided that may be employed in multicarrier communications to improve the efficiency of error correction using symbol-oriented error correction methodologies, by reducing the number of error correction code symbols (102, 104 . . . ) that are received in error that result from a single channel error. More specifically, in this technique, bits from the symbols are allocated among the channels in such a way as to minimize the number of respective channels that are allocated bits belonging to more that one respective symbol during a respective transmission period.

Claims

1. In digital communications using multicarrier modulation, a method of reducing forward error correction coding (FECC) symbol errors comprising:

providing a plurality of FECC symbols, each FECC symbol containing a number of bits;

providing a plurality of subchannels for modulating the bits; and

reordering the subchannels to reduce FECC symbol errors caused by bits from one subchannel being assigned to more than one FECC symbol.

2. In digital communications using multicarrier modulation, a system for reducing forward error correction coding (FECC) symbol errors comprising:

means for providing a plurality of FECC symbols, each FECC symbol containing a number of bits;

means for providing a plurality of subchannels for modulating the bits; and

means for reordering the subchannels to reduce FECC symbol errors caused by bits from one subchannel being assigned to more than one FECC symbol.

3. In digital communications using multicarrier modulation, a forward error correction coding (FECC) symbol error reduction system comprising:

a plurality of FECC symbols, each FECC symbol containing a number of bits;

a plurality of subchannels for modulating the bits; and

a transceiver configured to reordering the subchannels to reduce FECC symbol errors caused by bits from one subchannel being assigned to more than one FECC symbol.