Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection
First Claim
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1. A data transmission circuit, comprising:
- a first bus segment of a data bus;
a second bus segment of said data bus; and
a first switching circuit connected between said first and second segments of said data bus;
a second switching circuit connected between said second segment of said data bus and a third segment of said data bus;
wherein said first switching circuit is configured to selectively connect said first and second segments of said data bus such that when said first switching circuit is in a first state, said first switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, when said first switching circuit is in a second state, said second bus segment is disconnected from said first bus segment and data is passed through from said first bus segment to at least one I/O circuit and from said at least one I/O circuit to said first bus segment, said second switching circuit is configured to selectively connect said second and third segments of said data bus such that when said second switching circuit is in a first state, said second switching circuit passes data through from said second bus segment to said third bus segment and from said third bus segment to said second bus segment, and when said second switching circuit is in a second state, said third bus segment is disconnected from said second bus segment and data is passed through from said second bus segment to at least one I/O circuit and from said at least one I/O circuit to said second bus segment.
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Abstract
A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
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Citations
122 Claims
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1. A data transmission circuit, comprising:
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a first bus segment of a data bus;
a second bus segment of said data bus; and
a first switching circuit connected between said first and second segments of said data bus;
a second switching circuit connected between said second segment of said data bus and a third segment of said data bus;
whereinsaid first switching circuit is configured to selectively connect said first and second segments of said data bus such that when said first switching circuit is in a first state, said first switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, when said first switching circuit is in a second state, said second bus segment is disconnected from said first bus segment and data is passed through from said first bus segment to at least one I/O circuit and from said at least one I/O circuit to said first bus segment, said second switching circuit is configured to selectively connect said second and third segments of said data bus such that when said second switching circuit is in a first state, said second switching circuit passes data through from said second bus segment to said third bus segment and from said third bus segment to said second bus segment, and when said second switching circuit is in a second state, said third bus segment is disconnected from said second bus segment and data is passed through from said second bus segment to at least one I/O circuit and from said at least one I/O circuit to said second bus segment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A data transmission circuit, comprising:
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a first bus segment of a data bus;
a second bus segment of said data bus; and
a first switching circuit connected between said first and second segments of said data bus, wherein said first switching circuit is configured to selectively connect said first and second segments of said data bus such that when said first switching circuit is in a first state, said first switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, when said first switching circuit is in a second state, said second bus segment is disconnected from said first bus segment and data is passed through from said first bus segment to at least one I/O circuit and from said at least one I/O circuit to said first bus segment, and when said first switching circuit receives a command selecting at least one attached I/O circuit for point-to-point communications, said first switching circuit selects said second state to disconnect said first bus segment from said second bus segment, and passes data between said first bus segment and said at least one attached selected I/O circuit.
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17. A data transmission circuit, comprising:
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a first bus segment of a data bus;
a second bus segment of said data bus; and
a first switching circuit connected between said first and second segments of said data bus, wherein said first switching circuit is configured to selectively connect said first and second segments of said data bus such that when said first switching circuit is in a first state, said first switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, when said first switching circuit is in a second state, said second bus segment is disconnected from said first bus segment and data is passed through from said first bus segment to at least one I/O circuit and from said at least one I/O circuit to said first bus segment, said data bus is a first data bus having a first number of data paths, said first switching circuit is further configured to connect to a second data bus having a second number of data paths, and said first switching circuit is connected between said first and second data buses for selectively receiving data on said first data bus and placing said data on said second data bus and selectively receiving data on said second data bus and placing said data on said first data bus. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A data transfer interface, comprising:
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a first bus segment of a data bus;
a second bus segment of said data bus; and
an interface circuit connected between said first and second segments of said data bus;
wherein said interface circuit includes a switching circuit configured to selectively connect said first and second segments of said data bus such that when said switching circuit is in a first state, said switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and when said switching circuit is in a second state, said interface circuit receives and transmits data on said data bus and said second bus segment is disconnected from said first bus segment, and when said interface circuit receives a command selecting the interface circuit for point-to-point communications, said interface circuit selects said second state of said switching circuit to disconnect said first bus segment from said second bus segment, and performs at least one of receiving and transmitting data on said data bus using said first bus segment. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. An data transfer interface, comprising:
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a first data bus having a first number of data paths, said first data bus comprising;
a first bus segment; and
a second bus segment;
a second data bus having a second number of data paths; and
an interface circuit connected between said first segment of said data bus, said second segment of said first data bus, and said second data bus;
wherein said interface circuit includes a switching circuit configured to selectively connect said first and second segments of said data bus such that when said switching circuit is in a first state, said switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and when said switching circuit is in a second state, said interface circuit receives and transmits data on said data bus and said second bus segment is disconnected from said first bus segment, and said interface circuit selectively receives data on said first data bus and places said data on said second data bus, and selectively receives data on said second data bus and places said data on said first data bus. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A memory module, comprising:
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at least one memory device; and
a data transfer interface for connection to a segmented data bus, said data transfer interface being coupled to said at least one memory device and comprising;
a first segment of said data bus;
a second segment of said data bus; and
an interface circuit configured for connection between said first and second segments of said data bus, wherein said interface circuit includes a switching circuit configured to selectively connect said first and second segments of said data bus such that when said switching circuit is in a first state, said switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and when said switching circuit is in a second state, said interface circuit receives and transmits data on said data bus and said second bus segment is disconnected from said first bus segment.
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63. A memory system, comprising:
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at least one memory device; and
a data transfer interface connected to a first segmented data bus and to said at least one memory device by a second data bus, said data transfer interface comprising;
a first segment of said first data bus;
a second segment of said first data bus; and
an interface circuit connected between said first and second segments of said first data bus, wherein said interface circuit includes a switching circuit configured to selectively connect said first and second segments of said first data bus such that when said switching circuit is in a first state, said switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and when said switching circuit is in a second state, said interface circuit receives and transmits data on said first data bus and said second bus segment is disconnected from said first bus segment. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87)
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88. A data exchange system, comprising:
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a data bus having a plurality of bus segments; and
a plurality of system devices each connected to said first data bus, at least one of said system devices including a switching circuit connected between first and second bus segments of said data bus for selectively passing data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and for selectively disconnecting said second bus segment from said first bus segment to permit point-to-point data communications between said at least one system device and another system device using one of said first and second bus segments;
wherein a switchable terminator is included in at least one of said plurality of system devices. - View Dependent Claims (89, 90, 91, 92, 93, 94, 95, 96, 97)
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98. A processor system comprising;
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a processor;
at least one memory subsystem connected to said processor; and
a segmented bus which connects each of a controller and at least one memory subsystem interface circuit of said at least one memory subsystem;
whereby said memory subsystem interface circuit couples at least one memory device to said segmented bus, said memory subsystem interface circuit including a conversion circuit and a switching circuit, said conversion circuit receiving data from said segmented bus, converting it to data which can be processed by said at least one memory device, receiving data from said at least one memory device and converting it to data which can be transmitted over said segmented bus, said switching circuit being connected between first and second bus segments of said segmented bus such that when said switching circuit is in a first state, said switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, and when said switching circuit is in a second state, said interface circuit receives and transmits data on said first data bus and said second bus segment is disconnected from said first bus segment. - View Dependent Claims (99, 100, 101, 102)
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103. A method of data communication between devices in an electronic circuit, comprising:
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connecting at least one switching circuit between segments of a data bus;
selectively passing data on said data bus through from a first bus segment to a second bus segment and from said second bus segment to said first bus segment, said selective passing of data being performed using said switching circuit, whereby when said data passing is not selected said switching circuit disconnects said first bus segment from said second bus segment to permit point-to-point data communications using one of said first and second bus segments wherein said selective passing of data includes configuring said at least one switching circuit to pass data during WRITE operations.
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104. A method of data communication between devices in an electronic circuit, comprising:
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connecting at least one switching circuit between segments of a data bus; and
selectively passing data on said data bus through from a first bus segment to a second bus segment and from said second bus segment to said first bus segment, said selective passing of data being performed using said switching circuit, whereby when said data passing is not selected said switching circuit disconnects said first bus segment from said second bus segment to permit point-to-point data communications using one of said first and second bus segments;
wherein said selective passing of data includes configuring said at least one switching circuit to pass data between a memory controller and a selected I/O device during READ operations.
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105. A method of data communication between devices in an electronic circuit, comprising:
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connecting at least one switching circuit between segments of a data bus; and
selectively passing data on said data bus through from a first bus segment to a second bus segment and from said second bus segment to said first bus segment, said selective passing of data being performed using said switching circuit, whereby when said data passing is not selected said switching circuit disconnects said first bus segment from said second bus segment to permit point-to-point data communications using one of said first and second bus segments;
wherein said selective passing of data includes configuring said at least one switching circuit to pass data between a memory controller and a selected I/O device during WRITE operations.
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106. A method of data communication between devices in an electronic circuit, comprising:
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connecting a first set of I/O pins of an interface circuit to a first segment of a data bus;
connecting a second set of I/O pins of said interface circuit to a second segment of said data bus;
receiving and transmitting data on at least said first segment of said data bus using at least said first set of I/O pins; and
selectively passing data on said data bus through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, said selective passing of data being performed using a switching circuit;
wherein when said data passing is not selected said switching circuit disconnects said first bus segment from said second bus segment to permit point-to-point data communications using one of said first and second bus segments.
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107. A method of data communication between devices in an electronic circuit, comprising:
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connecting an interface circuit having first and second sets of I/O pins to respective first and second segments of a first data bus that operates at a first data rate;
connecting said interface circuit to a second data bus that operates at a second data rate;
receiving and transmitting data on said first data bus using said first and second sets of I/O pins;
receiving and transmitting data on said second data bus;
selectively converting data received from one of said first and second data buses for use on the other of said first and second data buses; and
selectively passing data on said first data bus through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, said selective passing of data being performed using a switching circuit, whereby when said data passing is not selected said switching circuit disconnects said first bus segment from said second bus segment to permit point-to-point data communications using one of said first and second bus segments. - View Dependent Claims (108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122)
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Specification