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Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection

  • US 6,871,253 B2
  • Filed: 06/29/2001
  • Issued: 03/22/2005
  • Est. Priority Date: 12/22/2000
  • Status: Active Grant
First Claim
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1. A data transmission circuit, comprising:

  • a first bus segment of a data bus;

    a second bus segment of said data bus; and

    a first switching circuit connected between said first and second segments of said data bus;

    a second switching circuit connected between said second segment of said data bus and a third segment of said data bus;

    wherein said first switching circuit is configured to selectively connect said first and second segments of said data bus such that when said first switching circuit is in a first state, said first switching circuit passes data through from said first bus segment to said second bus segment and from said second bus segment to said first bus segment, when said first switching circuit is in a second state, said second bus segment is disconnected from said first bus segment and data is passed through from said first bus segment to at least one I/O circuit and from said at least one I/O circuit to said first bus segment, said second switching circuit is configured to selectively connect said second and third segments of said data bus such that when said second switching circuit is in a first state, said second switching circuit passes data through from said second bus segment to said third bus segment and from said third bus segment to said second bus segment, and when said second switching circuit is in a second state, said third bus segment is disconnected from said second bus segment and data is passed through from said second bus segment to at least one I/O circuit and from said at least one I/O circuit to said second bus segment.

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