Pipelined parallel programming operation in a non-volatile memory system

• US 6,871,257 B2
• Filed: 02/22/2002
• Issued: 03/22/2005
• Est. Priority Date: 02/22/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Cedar, Yoram
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US10/081,375
• Publication Number:
  US 20030163629A1
• Time in Patent Office: 1,124 Days
• Field of Search: 711/103, 711/168, 711/169, 711/150, 365/185.11, 365/189.04, 365/189.05, 365/230.03, 710/53
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

Claims

1. A memory system circuit, comprising:

a controller comprising a first and a second data buffer connectable to receive host data from external to the memory system; and

a memory comprising a plurality of independently controllable non-volatile data storage sections connectable to the controller to receive data,

wherein, concurrently with the programming of data into a first of the data storage sections, data is transferable from either of said data buffers to a second of the data storage sections, and

wherein, concurrently with the transferring of data from one of said data buffers to the second of the data storage sections, host data from external to the memory system can be received into the other of said data buffers.

2. The memory system circuit of claim 1, further comprising:

a bus connected to transfer data between the controller and the data storage sections whereby data is transferable to the second data storage section while data is being programmed into the first data storage section.

3. The memory system circuit of claim 2, wherein each of the data storage sections comprises a data register wherein data transferred from the controller is stored.

4. The memory system circuit of claim 3, wherein each of the data storage sections further comprises an array of non-volatile storage units into which data stored in the data register is programmed.

5. The memory system circuit of claim 3, wherein each of the data storage sections further comprises a RAM memory section connected to store a copy of the data transferred into the data register.

6. The memory system circuit of claim 1, wherein the controller, the first data storage section and the second data storage section are on separate chips.

7. The memory system circuit of claim 1, wherein the first data storage section and the second data storage section are on a single chip.

8. The memory system circuit of claim 1, wherein the controller, the first data storage section and the second data storage section are on a single chip.

9. The memory system circuit of claim 1, wherein the controller, the first data storage section and the second data storage section are part of a single card structure removably attachable to a host.

10. The memory system circuit of claim 1, wherein the controller is embedded in a host and wherein the first data storage section and the second data storage section are part of a single card structure removably attachable to the host.

11. The system circuit of claim 1, wherein subsequent to the transfer of a data set from one of the buffers to one of the data storage sections, during the programming of said data set into said one of the data storage sections, a copy of said data set is maintained in said one of the buffers until said programming of said data set into said one of the data storage sections is completed.

12. The system circuit of claim 1, wherein subsequent to the transfer of a first data set from one of the buffers to one of the data storage sections, during the programming of the first data set into said one of the data storage sections, a second data set from external to the memory system is received in said one of the buffers prior to the completion of said programming of said data set into said one of the data storage sections.

13. The system circuit of claim 1, wherein said programming of data into a first of the data storage sections comprises the concurrent programming of multiple sectors of data.

14. A method of operating a non-volatile memory system comprising a controller including a plurality of data buffers and a memory including a plurality of independently controllable non-volatile data storage sections, the method comprising:

transfening a first set of data from an external source to a first of the data buffers;

transferring said first set of data from the first data buffer to a first of the data storage sections;

programming the first set of data into the first storage section;

transferring a second set of data from the external source to a second of the data buffers concurrently with said transferring said first set of data from the first data buffer to a first of the data storage sections; and

transferring said second set of data from the second data buffer to a second of the data storage sections concurrently with said programming the first set of data into the first storage section.

15. The method of claim 14, further comprising:

subsequent to the transferring the second set of data, programming the second set of data into the second storage section, wherein programming the second set of data starts during the programming the first set of data.

16. The method of claim 15, further comprising:

subsequent to the programming the first set of data, performing an erase operation in the first storage section, wherein the erase operation starts during the programming the second set of data.

17. The method of claim 14, wherein subsequent to said transferring said first set of data from the first data buffer to a first of the data storage sections, a copy of said first data set is maintained in said first buffers until said programming the first set of data into the first storage section is completed.

18. The method of claim 14, further comprising:

subsequent to said transferring said first set of data from the first data buffer to a first of the data storage sections, transferring a third set from the external source to the first data buffers prior to the completion of said programming the first set of data into the first storage section.

19. The method of claim 14, wherein said data sets comprise multiple sectors of data and wherein said programming comprises the concurrent programming of multiple sectors of data.