Integrated circuit random access memory capable of automatic internal refresh of memory array

• US 6,871,261 B1
• Filed: 11/15/2001
• Issued: 03/22/2005
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US09/999,563
• Time in Patent Office: 1,223 Days
• Field of Search: 711/105, 711/106, 711/155, 711/158, 711/159, 711/160, 711/167, 711/168, 365/189.01, 365/233
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No onboard cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Claims

1. A random access memory integrated circuit responsive to an externally supplied clock input, the random access memory integrated circuit comprising:

a dynamic memory array configured in one or more banks, wherein the dynamic memory array requires periodic refreshing to maintain data;

and

one or more refresh control circuits generating refresh requests inside the random access memory integrated circuit, the dynamic memory array configured to receive read and write access requests, wherein the read or write access requests have priority over pending refresh requests, wherein one pending refresh request to one of the banks is retired on any clock cycle not requiring an access of that bank, the refresh completing in the clock cycle, the read access requests initiating an access to the dynamic memory array without first determining whether data is available from outside the dynamic memory array, thereby avoiding a delay associated with such determination.

2. The random access memory integrated circuit of claim 1 wherein each of the one or more banks has a one to one correspondence with one of the one or more refresh control circuits, each refresh control circuit controlling refresh of the bank coupled thereto.

3. The random access memory integrated circuit of claim 1 wherein:

the dynamic memory array is configured in two or more banks, each of the two or more banks having a one to one correspondence with one of two or more refresh control circuits, each refresh control circuit controlling refresh of the bank coupled thereto; and

wherein during the clock cycle for which one bank of the dynamic memory array executes a read or a write operation, at least another bank may execute a refresh operation during the same clock cycle.

4. The random access memory integrated circuit of claim 3 wherein during the clock cycle for which one bank executes a read or a write operation, two other banks may simultaneously execute refresh operations.

5. The random access memory integrated circuit of claim 3 further comprising:

an address bus coupled to each of the banks, each of the banks configured to receive an independent address, wherein at least one bit of a read or write access address is used to select the bank for read or write access.

6. The random access memory integrated circuit of claim 5 wherein the bit is selected from among low-order address bits.

7. The random access memory integrated circuit of claim 5 wherein the bit changes state frequently.

8. The random access memory integrated circuit of claim 5 wherein the choice of the bit of the address allows the banks to share read and write accessing such that no one bank requires excessive accessing, the sharing of the read and write accessing thereby allowing each bank to meet refresh requirements.

9. The random access memory integrated circuit of claim 8 wherein excessive accessing includes read or write accessing more than 255 clock cycles of each 256 clock cycles.

10. The random access memory integrated circuit of claim 3, wherein each refresh control circuit is configured to receive an input from a decoder, the decoder producing one refresh request after a predetermined number of external clock cycles, the refresh requests generated independent of an elapsed time counter.

11. The random access memory integrated circuit of claim 3, wherein each of the refresh control circuit inputs is coupled to receive an output from a decoder, the decoder coupled to receive an input from a wrap around clock cycle counter.

12. The random access memory integrated circuit of claim 11 wherein the decoder is a counts 0, 64, 128, 192 decoder and the wrap around clock cycle counter is a divide by 256 wrap around clock cycle counter.

13. The random access memory integrated circuit of claim 11 wherein the wrap around clock cycle counter increments once every clock cycle and provides an input to the decoder, the wrap around clock cycle counter in combination with the decoder causing the decoder to sequentially provide a plurality of outputs, each output configured to be received by one of the refresh control circuits, the decoder providing decoded counts that are a specific number of clock cycles apart.

14. The random access memory integrated circuit of claim 13 wherein each output is received by a designated wrap around refresh request counter.

15. The random access memory integrated circuit of claim 13 wherein the specific number of clock cycles is more than a maximum number of queued refresh requests queued in any one refresh control circuit for any bank.

16. The random access memory integrated circuit of claim 15 wherein the maximum number of queued refresh requests in combination with the specific number of clock cycles prevents a sequence of external read or write cycles from causing more than two banks to refresh on the same clock cycle.

17. The random access memory integrated circuit of claim 3 wherein each refresh control circuit includes:

a wrap around refresh request counter that increments for each refresh request; and

a wrap around refresh address counter that increments in response to a refresh of a bank associated thereto; and

a row address comparator coupled to the wrap around refresh request counter and to the wrap around refresh address counter, an inequality between a count in the wrap around refresh request counter and a count in the wrap around refresh address counter indicating a pending refresh requirement for the bank associated with the refresh control circuit.

18. The random access memory integrated circuit of claim 17 wherein the wrap around refresh request counter is one of a plurality of wrap around refresh request counters within the random access memory integrated circuit, the plurality of wrap around refresh request counters incrementing at different times to stagger refresh operations of the banks whereby the noise generated is reduced from that which would occur if more banks refreshed simultaneously.

19. The random access memory integrated circuit of claim 18 wherein each of the wrap around refresh request counters is coupled to a decoder, each wrap around refresh request counter receiving a different output from the decoder, the different decoder outputs being responsive to different counts in different cycles thereby causing the incrementing of the plurality of wrap around refresh request counters at different times to stagger the refresh operations of the banks.

20. The random access memory integrated circuit of claim 3 further comprising:

a row address multiplexer coupled to an address bus, the row address

multiplexer receiving at least one bit of a read or write access address to select

a bank of the one or more banks for a read or write access.

21. The random access memory integrated circuit of claim 3 wherein each refresh control circuit is coupled to a wrap around clock cycle counter having an output that is decoded, wherein each decoded output toggles once for every predetermined number of clock cycles and is provided to a wrap around refresh request counter within each refresh control circuit, the wrap around refresh request counter coupled to receive the decoded output of the wrap around clock cycle counter and to increment one count each time the decoder output toggles, each refresh control circuit further including a wrap around refresh address counter incrementing in response to a refresh of the bank associated thereto, an inequality between a count in the wrap around refresh request counter and a count in the wrap around refresh address counter associated with a same bank indicating a pending refresh requirement for that bank.

22. The random access memory integrated circuit of claim 21 wherein the wrap around refresh address counter divides by a number equal to the number of cycles required to refresh all rows in the bank associated thereto.

23. The random access memory integrated circuit of claim 22 wherein the number equal to the number of cycles is 256.

24. The random access memory integrated circuit of claim 21 wherein the wrap around refresh request counters are associated with different banks, the wrap around refresh request counters incrementing at different times to stagger refresh operations of the banks whereby the noise generated is reduced from that which would occur if more banks refreshed simultaneously.

25. The random access memory integrated circuit of claim 21 wherein the count of the wrap around refresh address counter provides an address to its respective bank, the address identifying a row of memory in that bank to be refreshed.

26. The random access memory integrated circuit of claim 21 wherein when the count of the wrap around refresh request counter of any bank exceeds the count of the wrap around refresh address counter of the corresponding bank by a predetermined number, a refresh flag asserts.

27. The random access memory integrated circuit of claim 21 wherein the inequality for each bank is determined by a row address comparator.

28. The random access memory integrated circuit of claim 3, wherein each bank is coupled to one of the refresh control circuits, and each bank is coupled to an independent row address bus thereby allowing at least one bank to perform a refresh operation and another bank to perform an access operation in the same clock cycle.

29. The random access memory integrated circuit of claim 1 wherein the random access memory integrated circuit outputs a refresh flag to indicate that internal refresh requirements are not being met.

30. The random access memory integrated circuit of claims 29 wherein the flag is output after a predetermined number of refresh requests are queued.

31. The random access memory integrated circuit of claim 30 wherein the predetermined number of queued refresh requests is at least two.

32. The random access memory integrated circuit of claim 30 wherein the predetermined number of queued refresh requests is less than but close to a specific number of clock cycles separating a toggling of a plurality of outputs from a decoder, each output from the decoder configured to be received by one of the refresh control circuits.

33. The random access memory integrated circuit of claim 1 wherein each refresh control circuit includes:

a wrap around refresh request counter that increments for each refresh request; and

a wrap around refresh address counter that increments in response to a refresh of a bank associated thereto; and

a row address comparator coupled to the wrap around refresh request counter and to the wrap around refresh address counter, an inequality between a count in the wrap around refresh request counter and a count in the wrap around refresh address counter indicating a pending refresh requirement for the bank associated with the refresh control circuit.

34. The random access memory integrated circuit of claim 33 wherein the count of the wrap around refresh address counter provides an address to its respective bank, the address identifying a row of memory in that bank to be refreshed.

35. The random access memory integrated circuit of claim 34 wherein each refresh control circuit includes a row address multiplexer, the row address multiplexer receiving the address identifying a row of memory in the bank to be refreshed and receiving a read or write address for a read or write access, the output of the row address multiplexer being a read or write address if a read or write access is required of that bank and, when a read or write access is not required and a refresh is required, the output of the row address multiplexer being a refresh address received from the wrap around refresh address counter.

36. The random access memory integrated circuit of claim 34 wherein the output of the wrap around refresh address counter is coupled to a row address multiplexer, the row address multiplexer configured to send the address identifying a row of memory in that bank to be refreshed if the bank is not performing a read or write access.

37. The random access memory integrated circuit of claim 33 wherein when the count of the wrap around refresh request counter of any bank exceeds the count of the wrap around refresh address counter of the corresponding bank by a predetermined number, a refresh flag asserts.

38. The random access memory integrated circuit of claim 37 wherein the predetermined number is 62.

39. A random access memory integrated circuit comprising:

a dynamic memory array configured in one or more banks, wherein the dynamic memory array requires periodic refreshing to maintain data; and

one or more refresh control circuits generating refresh requests inside the random access memory integrated circuit, the dynamic memory array configured to receive read and write access requests, wherein the read or write access requests have priority over pending refresh requests, wherein one pending refresh request to one of the banks is retired on a clock cycle not requiring an access of that bank, each refresh completing in the clock cycle, each access request reading data from or writing data to the dynamic memory array, whereby data is never read from or written to an on-board cache memory, thereby saving the area that the on-board cache memory would occupy.

40. The random access memory integrated circuit of claim 39 wherein the dynamic memory array is configured in two or more banks, each of the two or more banks having a one to one correspondence with one of two or more refresh control circuits, each refresh control circuit controlling refresh of the bank coupled thereto.

41. The random access memory integrated circuit of claim 40 wherein during the clock cycle for which one bank of the dynamic memory array executes a read or a write operation, at least another bank may execute a refresh operation during the same clock cycle.

42. The random access memory integrated circuit of claim 41 wherein during the clock cycle for which one bank executes a read or a write operation, two other banks may simultaneously execute refresh operations.

43. The random access memory integrated circuit of claim 41 further comprising:

an address bus coupled to each of the banks, wherein each of the address busses are configured to receive an independent address.

44. The random access memory integrated circuit of claim 43 wherein at least one bit of a read or write access address is used to select the bank for read or write access.

45. The random access memory integrated circuit of claim 44 wherein the bit is selected from among low-order address bits.

46. The random access memory integrated circuit of claim 44 wherein the bit changes state frequently.

47. A method of refreshing a dynamic memory array contained in a circuit, the dynamic memory array including one or more banks subject to a plurality of read and write accesses, the banks configured to hold data without requiring data duplication outside the banks other than data transferred from the dynamic memory array in one of the read accesses, the method comprising:

determining within the circuit containing the dynamic memory array when one of the banks within the dynamic memory array requires a refresh;

prioritizing read or write access requests over any pending refresh requests, wherein read access requests initiating an access to the dynamic memory array occur without a delay associated with determining whether the data is available from a location outside the dynamic memory array; and

retiring, within one clock cycle, one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the dynamic memory array on that clock cycle.

48. The method of claim 47 wherein the dynamic memory array includes two or more banks, the method further comprising:

controlling the refreshing with two or more refresh control circuits contained in the circuit, each bank controlled with the refresh control circuit coupled thereto, each refresh control circuit checking whether its respective bank is subject to a read or write access, the refresh control circuit retiring a pending refresh when its respective bank is not subject to the read or write access.

49. The method of claim 48 wherein there is a one to one correspondence between each bank and each refresh control circuit, each refresh control circuit controlling the refreshing of the bank coupled thereto.

50. The method of claim 48 further comprising:

selecting the bank to be read or written according to predetermined bits of a read or write access address received via an address bus coupled to each of the refresh control circuits.

51. The method of claim 50 wherein the predetermined bits include one of low order address bits, a least significant bit, a penultimate least significant bit, and bits that toggle frequently.

52. The method of claim 48 further comprising:

performing access operations and refresh operations on different banks during the same clock cycle.

53. The method of claim 52 wherein the number of banks performing access operations and refresh operations is limited to less than all banks to prevent corruption of data by power supply noise.

54. The method of claim 48 wherein each refresh control circuit includes a wrap around refresh request counter configured to increment to reflect a refresh request, the incrementing occurring such that only the wrap around refresh request counters coupled to one of the banks increment on any given clock cycle.

55. The method of claim 48 wherein each of the two or more banks is configured to receive a respective input from its respective refresh control circuit.

56. The method of claim 48 wherein each refresh control circuit receives an output from a decoder, the output of the decoder being received by a wrap around refresh request counter within each refresh control circuit and the decoder being configured to receive an input from a wrap around clock cycle counter.

57. The method of claim 56 wherein the wrap around clock cycle counter provides an input to the decoder, wherein every predetermined number of clock cycles, the wrap around clock cycle counter in combination with the decoder cause the decoder to sequentially toggle one of a plurality of outputs from the decoder, each of the plurality of outputs being received by a respective one of the refresh control circuits.

58. The method claim 57 wherein:

each output of the plurality of outputs is received by one of the wrap around refresh request counters; and

the predetermined number of clock cycles is more than a maximum number of queued refresh requests that can be queued in each refresh control circuit.

59. The method of claim 58 wherein the maximum number of queued refresh requests in combination with the predetermined number of clock cycles prevent a sequence of external read or write accesses from causing more than two banks to refresh on a same clock cycle.

60. The method claim 57 wherein the predetermined number of clock cycles is more than a maximum number of queued refresh requests within the wrap around refresh request counter in any one refresh control circuit for any of the banks.

61. The method of claim 60 wherein the predetermined number of clock cycles prevents more than two banks of the two or more banks from performing a refresh at the same time.

62. The method of claim 47 further comprising:

queuing refresh requests in a refresh control circuit coupled to each bank.

63. The method of claim 47 wherein the refresh control circuit generates refresh requests independent from an elapsed time determination, each refresh request generated as a function of a number of clock cycles received.