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Processor and method of executing a load instruction that dynamically bifurcate a load instruction into separately executable prefetch and register operations

  • US 6,871,273 B1
  • Filed: 06/22/2000
  • Issued: 03/22/2005
  • Est. Priority Date: 06/22/2000
  • Status: Expired due to Fees
First Claim
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1. A processor, comprising:

  • a plurality of registers;

    instruction processing circuitry that fetches an instruction sequence for execution, said instruction sequence including a load instruction and a preceding instruction that precedes said load instruction in program order, wherein said instruction processing circuitry, after fetching said instruction sequence for execution and prior to dispatching said load instruction for execution and responsive to detecting said load instruction within said fetched instruction sequence, translates said load instruction into separately executable prefetch and register instructions and thereafter dispatches said prefetch and register instructions for execution;

    a request bus coupled to lower level memory; and

    execution circuitry coupled to said request bus and coupled to receive dispatched instructions including sand prefetch, register, and preceding instructions from said instruction processing circuitry, wherein said execution circuitry executes at least said prefetch instruction out-of-order with respect to said preceding instruction to prefetch data and subsequently separately executes said register instruction to place said data into a register among said plurality of registers specified by said load instruction, wherein said execution circuitry executes said prefetch instruction by calculating a speculative target memory address utilizing contents of at least one register identified by said prefetch instruction, without regard for whether said contents will be modified between calculation of said speculative target memory address and execution of said register instruction, and by thereafter initiating a fetch, via said request bus, of said data from a memory location associated with said speculative target memory address.

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