Processor and method of executing a load instruction that dynamically bifurcate a load instruction into separately executable prefetch and register operations

• US 6,871,273 B1
• Filed: 06/22/2000
• Issued: 03/22/2005
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Moore, Charles Robert
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Huisman, David J.
• Application Number:
  US09/598,436
• Time in Patent Office: 1,734 Days
• Field of Search: 712/207
• US Class Current: 712/207
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A processor implementing an improved method for executing load instructions includes execution circuitry, a plurality of registers, and instruction processing circuitry. The instruction processing circuitry fetches a load instruction and a preceding instruction that precedes the load instruction in program order, and in response to detecting the load instruction, translates the load instruction into separately executable prefetch and register operations. The execution circuitry performs at least the prefetch operation out-of-order with respect to the preceding instruction to prefetch data into the processor and subsequently separately executes the register operation to place the data into a register specified by the load instruction. In an embodiment in which the processor is an in-order machine, the register operation is performed in-order with respect to the preceding instruction.

Claims

1. A processor, comprising:

a plurality of registers;

instruction processing circuitry that fetches an instruction sequence for execution, said instruction sequence including a load instruction and a preceding instruction that precedes said load instruction in program order, wherein said instruction processing circuitry, after fetching said instruction sequence for execution and prior to dispatching said load instruction for execution and responsive to detecting said load instruction within said fetched instruction sequence, translates said load instruction into separately executable prefetch and register instructions and thereafter dispatches said prefetch and register instructions for execution;

a request bus coupled to lower level memory; and

execution circuitry coupled to said request bus and coupled to receive dispatched instructions including sand prefetch, register, and preceding instructions from said instruction processing circuitry, wherein said execution circuitry executes at least said prefetch instruction out-of-order with respect to said preceding instruction to prefetch data and subsequently separately executes said register instruction to place said data into a register among said plurality of registers specified by said load instruction, wherein said execution circuitry executes said prefetch instruction by calculating a speculative target memory address utilizing contents of at least one register identified by said prefetch instruction, without regard for whether said contents will be modified between calculation of said speculative target memory address and execution of said register instruction, and by thereafter initiating a fetch, via said request bus, of said data from a memory location associated with said speculative target memory address.

2. The processor of claim 1, wherein said execution circuitry executes said register instruction in-order with respect to said preceding instruction.

3. The processor of claim 1, wherein said execution circuitry executes said register instruction out-of-order with respect to said preceding instruction.

4. The processor of claim 1, wherein said execution circuitry stores said data prefetched in response to said prefetch instruction in a temporary register.

5. The processor of claim 1, and further comprising a data hazard detector that, in response to detection of a hazard for said data, signals said protest to discard said data and said register instruction.

6. The processor of claim 1, wherein said prefetch and register instructions have a same operation code.

7. The processor of claim 6, wherein said prefetch and register instructions specify a same target register for said data and differ only in a value of a register operation field.

8. A method, said method comprising:

fetching an instruction sequence for execution, said instruction sequence including a load instruction and a preceding instruction that precedes said load instruction in program order;

in response to fetching said instruction sequence for execution and prior to execution of said load instruction, instruction processing circuitry detecting said load instruction within said fetched instruction sequence and translating said load instruction into separately executable prefetch and register instructions;

after the translating, the instruction processing circuitry dispatching the preceding instruction and the prefetch and register instructions for execution;

execution circuitry receiving the dispatched preceding instruction and the prefetch and register instructions from the instruction processing circuitry;

in response to receiving the dispatched prefetch instruction, the execution circuitry executing at least said prefetch instruction out-of-order with respect to said preceding instruction to prefetch data, wherein executing said prefetch instruction comprises;

the execution circuitry calculating a speculative target memory address utilizing contents of at least one register identified by the prefetch instruction without regard for whether said contents will be modified between calculation of said speculative target memory address and execution of said register instruction; and

thereafter the execution circuitry initiating a fetch via, a request bus coupled to lower level memory, of said data from a memory location associated with said speculative target memory address; and

thereafter, the execution circuitry separately executing said register instruction to place said data into a register specified by said load instruction.

9. The method of claim 8, and further comprising executing said register instruction in-order with respect to said preceding instruction.

10. The method of claim 8, and further comprising executing said register instruction out-of-order with respect to said preceding instruction.

11. The method of claim 8, wherein performing said prefetch comprises storing said data in a temporary register.

12. The method of claim 8, and further comprising:

detecting a data hazard for said data; and

in response to detection of said hazard for said data, discarding said data and said register instruction.

13. The method of claim 8, wherein translating said load instruction comprises translating said load instruction into prefetch and register instructions having a same operation code.

14. The method of claim 13, wherein said prefetch and register instructions specify a same target register for said data and differ only in a value of a register operation field.