Method of manufacturing transistor

• US 6,872,611 B2
• Filed: 02/26/2004
• Issued: 03/29/2005
• Est. Priority Date: 09/13/1999
• Status: Expired due to Term

• Current Assignee: Shindengen Electric Manufacturing Company Limited
• Original Assignee: Shindengen Electric Manufacturing Company Limited
• Inventors: Watanabe, Yuji, Takemori, Toshiyuki
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/785,960
• Publication Number:
  US 20040166619A1
• Time in Patent Office: 397 Days
• Field of Search: 438/197
• US Class Current: 438/197
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A technique is provided which makes it possible to reduce the area of a power MOSFET. A power MOSFET 1 according to the invention is a trench type in which a source region 27 is exposed on both of a substrate top surface 51 and an inner circumferential surface 52 of a trench 18. Since this makes it possible to provide contact between the source region 27 and a source electrode film 29 not only on the substrate top surface 51 but also on the inner circumferential surface 52 of the trench 18, source contact is provided with a sufficiently low resistance only on the substrate top surface, and the area of the device can be made smaller than that in the related art in which the source region 27 has been formed in a larger area.

Claims

1. A method of manufacturing a transistor, comprising the steps of:

diffusing an impurity on a top surface of a drain layer of a first conductivity type provided on a semiconductor layer to form a conductive region of a second conductivity type;

forming a trench having a bottom surface which is located deeper than a bottom surface of said conductive region;

forming a gate insulating film at least on a side surface of said trench;

forming a gate electrode material in said trench;

forming a source region of the first conductive type which is in contact with said gate insulating film and whose lower end is lower than the upper end of said gate electrode material, in an entire cross-section thereof, in said conductive region;

forming a film which consists of an insulating material having an upper end which is lower than the opening of said trench on said gate electrode material; and

exposing said source region on an upper part of the side, surface of said trench and forming a source electrode film in contact with said source region.

2. A method of manufacturing a transistor according to claim 1, wherein said step of forming a film which consists of said insulating material includes the steps of:

forming a first insulating film on a top surface of said gate electrode material, a side surface of said trench in the vicinity of the opening thereof and a top surface of said conductive region;

forming a second insulating film on a top surface of said first insulating film to fill the interior of said trench; and

removing an upper part of said second insulating film inside of said trench together with said first and second insulating films outside of said trench to expose said source region on an upper part of the side surface of said trench.

3. A method of manufacturing a transistor according to claim 2,

wherein said step of forming said gate electrode material includes the step of depositing polysilicon in said trench, and

wherein said step of forming said first insulating film includes the step of oxidizing a top surface of said gate electrode film, a side surface of said trench in the vicinity of the opening thereof and a top surface of said conductive region to form said first insulating film.