Semiconductor device having capacitors for reducing power source noise

• US 6,873,035 B2
• Filed: 05/02/2001
• Issued: 03/29/2005
• Est. Priority Date: 12/15/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Baba, Shinji, Watanabe, Masaki
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US09/846,272
• Publication Number:
  US 20020074669A1
• Time in Patent Office: 1,427 Days
• Field of Search: 257/686, 257/724, 257/777, 257/685, 257/723, 257/904, 257/778, 257/737, 438/109, 361/767, 361/766, 361/782, 361/734
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/535 : including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 257/924 : with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

A semiconductor device comprises a BGA substrate having one principal plane furnished with a large number of solder balls, the solder balls constituting a ball grid array; a semiconductor chip mounted on another principal plane of the BGA substrate, the semiconductor chip being electrically connected to the BGA substrate by metal wires; and chip capacitors mounted on the semiconductor chip to reduce power source noise.

Claims

1. A semiconductor device comprising:

a BGA substrate having one principal plane furnished with a large number of solder balls;

a first semiconductor chip having a first side and an opposite side, said first semiconductor chip including bumps and active regions formed on the first side, said first semiconductor chip being attached to another principal plane of said BGA substrate through the bumps; and

a first chip capacitor attached to the active regions of said first semiconductor chip,

wherein a thickness of said first chip capacitor is less than a thickness of the bumps.

2. The semiconductor device according to claim 1, further comprising:

a second semiconductor chip mounted on said opposite side of said active regions of said first semiconductor chip, said second semiconductor chip being electrically connected to said BGA substrate by metal wires; and

a second chip capacitor attached to said second semiconductor chip as well as a first chip capacitor attached to said active region of said first semiconductor chip, said second chip capacitor serving to reduce power source noise.

3. The semiconductor device according to claim 1, further comprising:

a conductive radiator attached to said another principal plane of said BGA substrate, said conductive radiator covering said first semiconductor chip; and

a shield plane incorporated in said BGA substrate, said shield plane constituting a shield of said first semiconductor chip in combination with said conductive radiator;

wherein said conductive radiator and said shield plane are connected to ground potential.

4. The semiconductor device according to claim 3, further comprising a heat transfer member interposed between said opposite side of said active regions of said semiconductor chip and said conductive radiator.

5. The semiconductor device according to claim 3, further comprising a radiating fin attached to an external surface of said conductive radiator.

6. The semiconductor device according to claim 1, wherein said first chip capacitor is disposed among the bumps.

7. A semiconductor device comprising:

a BGA substrate having one principal plane furnished with a large number of solder balls;

a first semiconductor chip having a first side and an opposite side, said first semiconductor chip including bumps and active regions formed on the first side, said first semiconductor chip being attached to another principal plane of said BGA substrate through the bumps; and

a first chip capacitor attached to the opposite side of said first semiconductor chip,

wherein said first semiconductor chip further includes vias extending from the active regions to the opposite side of said first semiconductor chip, and said first chip capacitor is electrically connected to the active regions through the vias.

8. The semiconductor device according to claim 7, further comprising:

a conductive radiator attached to said another principal plane of said BGA substrate, said conductive radiator covering said semiconductor chip; and

a shield plane incorporated in said BGA substrate, said shield plane constituting a shield of said semiconductor chip in combination with said conductive radiator;

wherein said conductive radiator and said shield plane are connected to ground potential.

9. The semiconductor device according to claim 8, further comprising a radiating fin attached to an external surface of said conductive radiator.

10. The semiconductor device according to claim 7, further comprising a mold resin covering said semiconductor chip and chip capacitor.

11. The semiconductor device according to claim 7, further comprising an under-fill resin for sealing said bumps.