Method for detecting the reliability of integrated semiconductor components at high temperatures

• US 6,873,170 B2
• Filed: 01/02/2004
• Issued: 03/29/2005
• Est. Priority Date: 07/23/2001
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Martin, Andreas, Smeets, David, Fazekas, Josef, Asam, Wilhelm, Hagen, Jochen Von
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R
• Application Number:
  US10/751,316
• Publication Number:
  US 20040140826A1
• Time in Patent Office: 452 Days
• Field of Search: 257/467, 257/48, 257/797, 257/E21.521, 737/77, 73765-769, 324/158, 324/252, 374/178, 374183-185, D10/77, 438/18
• US Class Current: 324/750.06
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/3173 Marginal testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications

Abstract

The invention relates to a device and a method for detecting the reliability of integrated semiconductor components. The device includes a carrier substrate for receiving an integrated semiconductor component that will be examined, a heating element, and a temperature sensor. The temperature sensor has at least a portion of a parasitic functional element of the semiconductor component. As a result, reliability tests can be carried out in a particularly accurate and space-saving manner.

Claims

1. A method for detecting a reliability of an integrated semiconductor component, which comprises:

using a temperature sensor including at least a portion of a parasitic functional element of the semiconductor component to perform a measurement mode for measuring a temperature that is caused by a heating element and that is actually present at the semiconductor component;

performing a stress mode for stressing the semiconductor component at least in a manner dependent on a temperature of the heating element; and

evaluating a failure instant of the semiconductor component at least in a manner dependent on the temperature that is caused by the heating element.

2. The method according to claim 1, which comprises:

during the stressing, altering an electrical parameter selected from a group consisting of a stress current density and a stress voltage in the semiconductor component; and

during the evaluating, taking the electrical parameter into account.

3. The method according to claim 1, which comprises:

during the measurement mode, impressing a very small measurement current on the temperature sensor.

4. The method according to claim 1, which comprises:

during the measurement mode, deriving a temperature that is actually present at the semiconductor component from a characteristic curve selected from a group consisting of an I/V characteristic curve of the parasitic functional element and a C/V characteristic curve of the parasitic functional element.

5. The method according to claim 1, which comprises:

performing the measurement mode and the stress mode separately from each other with respect to time.

6. The method according to claim 1, which comprises:

during the measurement mode, calibrating the heating element; and

during the stress mode, stressing the semiconductor component in a manner dependent on the heating element that has been calibrated.

7. The method according to claim 1, which comprises:

simultaneously performing the measurement mode and the stress mode.