Compensating for differences between clock signals

• US 6,873,195 B2
• Filed: 08/22/2001
• Issued: 03/29/2005
• Est. Priority Date: 08/22/2001
• Status: Expired due to Term

• Current Assignee: ARRIS Enterprises LLC (CommScope Holding Company, Inc.)
• Original Assignee: Bigband Networks Incorporated (II-VI Incorporated)
• Inventors: Dormitzer, Paul, Engelse, Willem, Robidoux, Raymond
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, HAI L
• Application Number:
  US09/935,209
• Publication Number:
  US 20030038660A1
• Time in Patent Office: 1,315 Days
• Field of Search: 327/162, 327/163, 327/141, 327145-147, 327152-156, 327250-253, 327269-271, 327/144, 375354-356, 375/362, 375/373, 375375-377
• US Class Current: 327/163
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A clock compensation circuit is provided. The circuit comprises a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals. The circuit further comprises a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals and a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.

Claims

1. A clock compensation circuit, comprising:

a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals;

a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals; and

a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the one of the plurality of internal logic clock signals based on the control signal.

2. The clock compensation circuit of claim 1, wherein the clock synchronization circuit comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals.

3. The clock compensation circuit of claim 1, wherein the one of the plurality of internal logic clock signals is matched in frequency to the sample clock.

4. The clock compensation circuit of claim 1, wherein the synchronization circuit receives an input clock signal on the order of 100 MHz and produces internal logic clock signals on the order of 20 MHz, 40 MHz, and 100 MHz.

5. The clock compensation circuit of claim 1, wherein the down converter channel comprises:

a first flip flop circuit coupled to receive the one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed by the multiplexer is in phase with the sample clock signal.

6. The clock compensation circuit of claim 1, wherein the down converter channel produces two selectable outputs that are 180 degrees out of phase.

7. A digital down converter, comprising:

a clock compensation circuit including;

a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals;

a phase comparator coupled to receive one of the plurality of internal logic clock signals and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals; and

a down converter channel coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the one of the plurality of internal logic clock signals based on the control signal.

8. The digital down converter of claim 7, wherein the clock synchronization circuit comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals.

9. The digital down converter of claim 7, wherein the one of the plurality of internal logic clock signals is matched in frequency to the sample clock.

10. The digital down converter of claim 7, wherein the synchronization circuit receives an input clock signal on the order of 100 MHz and produces internal logic clock signals on the order of 20 MHz, 40 MHz, and 100 MHz.

11. The digital down converter of claim 7, wherein the down converter channel comprises:

a first flip flop circuit coupled to receive the one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed by the multiplexer is in phase with the sample clock signal.

12. A clock compensation circuit, comprising:

an input for receiving an input clock signal;

a clock synchronization circuit coupled to receive the input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals;

a tapped delay line coupled to receive a first one of the plurality of internal logic clock signals and to generate a clock signal with a selected delay as an output clock signal;

a phase comparator coupled to receive a second one of the plurality of internal logic clock signals and a sample clock from an associated receiver and to generate a control signal based on a phase comparison of the second one of the plurality of internal logic clock signals and the sample clock; and

a down converter channel coupled to receive the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the second one of the plurality of internal logic clock signals based on the control signal.

13. The clock compensation circuit of claim 12, wherein the clock synchronization circuit comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals.

14. The clock compensation circuit of claim 12, wherein the clock divider receives a master clock signal on the order of 200 MHz and produces internal logic clock signals on the order of 20 MHz, 40 MHz, and 100 MHz.

15. The clock compensation circuit of claim 12, wherein the second one of the plurality of internal logic clock signals is matched in frequency to the sample clock.

16. The clock compensation circuit of claim 12, wherein the down converter channel comprises:

a first flip flop circuit coupled to receive the second one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the second one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed by the multiplexer is in phase with the sample clock signal.

17. A clock compensation circuit, comprising:

an input for receiving an input clock signal;

a clock synchronization circuit coupled to receive the input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals;

a phase comparator coupled to receive a first one of the plurality of internal logic clock signals and a sample clock from an associated receiver and to generate a control signal based on a phase comparison between the sample clock and the one of the plurality of internal logic clock signals;

a tapped delay line coupled to receive a second one of the plurality of internal logic clock signals and to generate a delayed clock signal for input to the associated receiver, wherein the delayed clock signal is synchronized with the sample clock; and

a down converter channel coupled to receive the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the first one of the plurality of internal logic clock signals based on the control signal.

18. The clock compensation circuit of claim 17, wherein the clock synchronization circuit comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals.

19. The clock compensation circuit of claim 17, wherein the first one of the plurality of internal logic clock signals is matched in frequency to the sample clock.

20. The clock compensation circuit of claim 17, wherein the down converter channel comprises:

a first flip flop circuit coupled to receive the first one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the first one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop circuit; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed by the multiplexer is in phase with the sample clock signal.

21. A communications system, comprising:

a plurality of receivers, wherein each receiver is coupled to receive a data signal and a clock signal;

a digital down conversion circuit, including;

a clock synchronization circuit coupled to receive an input clock signal, wherein the clock synchronization circuit generates a master clock signal and produces a plurality of internal logic clock signals;

a plurality of phase comparators, wherein each phase comparator is coupled to receive a first one of the plurality of internal logic clock signals and a sample clock signal from an associated one of the plurality of receivers and to generate a control signal based on a comparison of the phase of the first one of the plurality of internal logic clock signals with the sample clock signal; and

a plurality of down converter channels, wherein each of the plurality of down converter channels is coupled to receive the plurality of internal logic clock signals and the control signal and passes data from the data signal in phase with the sample clock signal.

22. The communications system of claim 21, wherein the synchronization circuit comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal therefrom; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals therefrom.

23. The communications system of claim 21, wherein each of the down converter channels comprises:

a first flip flop circuit coupled to receive the first one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the first one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop circuit; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed is in phase with the sample clock signal.

24. The communications system of claim 21, further comprising a tapped delay line coupled to receive a second one of the plurality of internal logic clock signals and to generate a plurality of output clock signals with a selected delay based on the second one of the plurality of internal logic clock signals, wherein each of the plurality of output clock signals is used by the associated receiver to generate the sample clock.

25. A method of generating a timing signal, the method comprising:

receiving an input clock signal;

receiving a sample clock from an associated receiver;

generating a master clock signal from the input clock signal;

generating a plurality of internal logic clock signals from the master clock signal;

comparing the phase of one of the plurality of internal logic clock signals to the phase of the received sample clock;

when the one of the plurality of internal logic clock signals is in phase with the received sample clock, selecting a data signal that is clocked on the rising edge of the one of the plurality of internal logic clock signals;

when the one of the plurality of internal logic clock signals is out of phase with the received sample clock, selecting the data that is clocked on the falling edge of the one of the plurality of internal logic clock signals; and

passing the selected data signal to the associated receiver.

26. A method of generating a timing signal, comprising:

receiving an input clock signal;

receiving a sample clock from an associated receiver;

generating a master clock signal from the input clock signal;

generating a plurality of internal logic clock signals from the master clock signal;

comparing the phase of one of the plurality of internal logic clock signals to the phase of the received sample clock;

generating a plurality of delayed clock signals from another one of the plurality of logic clock signals, wherein each of the plurality of delayed clock signals is synchronized with the sample clock of an associated receiver;

when the one of the plurality of internal logic clock signals is in phase with the received sample clock, selecting a data signal that is clocked on the rising edge of the one of the plurality of internal logic clock signals;

when the one of the plurality of internal logic clock signals is out of phase with the received sample clock, selecting the data that is clocked on the falling edge of the one of the plurality of internal logic clock signals; and

passing the selected data signal to the associated receiver.

27. A communications system, comprising:

a plurality of analog to digital converters;

a digital down converter coupled to receive an input clock signal from one of the plurality of analog to digital converters, wherein the digital down converter includes;

a clock synchronization circuit coupled to receive the input clock signal and to generate a master clock signal and a plurality of internal logic clock signals;

a plurality of phase comparators, wherein each phase comparator is coupled to receive a first one of the plurality of internal logic clock signals and a sample clock from an associated receiver, and wherein each phase comparator generates a control signal based on a phase comparison between the sample clock and the first one of the plurality of internal logic clock signals;

a plurality of down converter channels, wherein each down converter channel is coupled to receive each of the plurality of internal logic clock signals and the control signal and to pass data in phase with the sample clock using the first one of the plurality of internal logic clock signals based on the control signal;

a plurality of receivers, each receiver associated with one of the plurality of phase comparators and one of the plurality of down converter channels; and

a tapped delay line coupled to a second one of the plurality of internal logic clock signals and to generate a clock signal with a selected delay as an output clock signal for each of the plurality of receivers.

28. The system of claim 27, wherein each of the plurality of down converter channels comprises:

a first flip flop circuit coupled to receiving the first one of the plurality of internal logic clock signals and to pass a first data signal with a first phase;

a second flip flop circuit coupled to receive the first one of the plurality of internal logic clock signals and to pass a second data signal 180 degrees out of phase with the data signal output by the first flip flop circuit; and

a multiplexer coupled to receive the first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed is in phase with the sample clock signal.

29. The system of claim 27, wherein each of the clock synchronization circuits comprises:

a phase-locked loop coupled to receive the input clock signal and to generate the master clock signal; and

a clock divider coupled to receive the master clock signal and to produce the plurality of internal logic clock signals.

30. A clock compensation circuit, comprising:

a clock synchronization circuit coupled to receiving an input clock signal, wherein the clock synchronization circuit generates a plurality of internal logic clock signal of different frequencies;

a phase comparator coupled to receive at least one of the internal logic clock signal and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the at least one internal logic clock signal; and

a down converter channel coupled to receive the at least one internal logic clock signal and the control signal and to pass data in phase with the sample clock using the internal logic clock signal based on the control signal.

31. A clock compensation circuit, comprising:

a phase comparator coupled to receive a first clock signal and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the first clock signal; and

a data channel coupled to receive the first clock signal and the control signal and to pass data in phase with the sample clock using the first clock signal based on the control signal.

32. A clock compensation circuit, comprising:

a phase alignment circuit which includes;

a phase comparator coupled to receive a first clock signal and a sample clock from an associated receiver, wherein the phase comparator generates a control signal based on a phase comparison between the sample clock and the first clock signal; and

a multiplexer to receive first and second data signals and the control signal, the multiplexer selectively outputting either the first data signal or the second data signal based on the control signal such that the data signal passed by the multiplexer is in phase with the sample clock signal.