Nonvolatile memory system, semiconductor memory, and writing method
First Claim
1. A nonvolatile memory comprising:
- a plurality of nonvolatile memory cells;
a controller;
a plurality of latch circuits;
a plurality of bit lines; and
a plurality of word lines, wherein each of said plurality of nonvolatile memory cells has a first terminal and a second terminal, wherein each of said word lines are coupled to said first terminals of corresponding ones of said plurality of nonvolatile memory cells, wherein each of said bit lines are coupled to said second terminals of corresponding ones of said plurality of nonvolatile memory cells in parallel, and to a corresponding one of said latch circuits, wherein each of said plurality of nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones, wherein nonvolatile memory cells belonging to said first ones have already stored first data therein, and each of said nonvolatile memory cells belonging to said first ones has one of a first state and a second state according to said first data, wherein each of nonvolatile memory cells belonging to said second ones have said first state, and wherein prior to a program operation of said first ones and said second ones, first latch circuits coupled to said first ones via first bit lines and second latch circuits coupled to said second ones via second bit lines are set with first data and second data, respectively, and wherein after setting of the first and second latch circuits with said first and said second data, said program operation of said first and said second ones are programmed in parallel bit by bit in response to said first data and said second data set in said first and second latch circuits.
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Abstract
A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
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Citations
9 Claims
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1. A nonvolatile memory comprising:
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a plurality of nonvolatile memory cells;
a controller;
a plurality of latch circuits;
a plurality of bit lines; and
a plurality of word lines, wherein each of said plurality of nonvolatile memory cells has a first terminal and a second terminal, wherein each of said word lines are coupled to said first terminals of corresponding ones of said plurality of nonvolatile memory cells, wherein each of said bit lines are coupled to said second terminals of corresponding ones of said plurality of nonvolatile memory cells in parallel, and to a corresponding one of said latch circuits, wherein each of said plurality of nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones, wherein nonvolatile memory cells belonging to said first ones have already stored first data therein, and each of said nonvolatile memory cells belonging to said first ones has one of a first state and a second state according to said first data, wherein each of nonvolatile memory cells belonging to said second ones have said first state, and wherein prior to a program operation of said first ones and said second ones, first latch circuits coupled to said first ones via first bit lines and second latch circuits coupled to said second ones via second bit lines are set with first data and second data, respectively, and wherein after setting of the first and second latch circuits with said first and said second data, said program operation of said first and said second ones are programmed in parallel bit by bit in response to said first data and said second data set in said first and second latch circuits. - View Dependent Claims (2, 3, 4, 5)
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6. A nonvolatile memory comprising:
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a plurality of nonvolatile memory cells;
a controller;
a plurality of bit lines;
a plurality of word lines; and
a latch unit, wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges, a first threshold voltage range of said plurality of threshold voltage ranges indicates an erase state and a second threshold voltage range of said plurality of threshold voltage ranges indicates a program state, and has a first terminal, a second terminal and a well region, wherein each of said word lines couples to said first terminals of corresponding ones of said nonvolatile memory cells, wherein each of said bit lines couples to said second terminals of corresponding ones of said nonvolatile memory cells in parallel, wherein each of said nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones, wherein each of said threshold voltages of nonvolatile memory cells belonging to said first ones is within either said first threshold voltage range or said second threshold voltage range according to stored first data, wherein each of said threshold voltages of nonvolatile memory cells belonging to said second ones is within said first threshold voltage range, wherein said well regions of adjacent nonvolatile memory cells coupled to one word line are connected, wherein said controller carries out a program operation, in response to receiving a first command with a second data, wherein in said program operation, said controller selects one word line, reads out first data from first ones coupled to selected word line, and sets said first data and said second data to said latch unit, wherein after setting said first data and said second data to said latch unit in said program operation, said controller carries out supply of a first voltage to said selected word line so that said first ones and second ones are programmed in parallel in response to said first data and said second data set in said latch unit. - View Dependent Claims (7, 8, 9)
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Specification