Nonvolatile memory system, semiconductor memory, and writing method

• US 6,873,552 B2
• Filed: 10/09/2003
• Issued: 03/29/2005
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Engineering Corp, Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US10/681,280
• Publication Number:
  US 20040114434A1
• Time in Patent Office: 537 Days
• Field of Search: 365/171, 365/185.24, 365/189.05, 365/185.29, 365/185.02, 365/230.08
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory comprising:

a plurality of nonvolatile memory cells;

a controller;

a plurality of latch circuits;

a plurality of bit lines; and

a plurality of word lines,

wherein each of said plurality of nonvolatile memory cells has a first terminal and a second terminal,

wherein each of said word lines are coupled to said first terminals of corresponding ones of said plurality of nonvolatile memory cells,

wherein each of said bit lines are coupled to said second terminals of corresponding ones of said plurality of nonvolatile memory cells in parallel, and to a corresponding one of said latch circuits,

wherein each of said plurality of nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones,

wherein nonvolatile memory cells belonging to said first ones have already stored first data therein, and each of said nonvolatile memory cells belonging to said first ones has one of a first state and a second state according to said first data,

wherein each of nonvolatile memory cells belonging to said second ones have said first state, and

wherein prior to a program operation of said first ones and said second ones, first latch circuits coupled to said first ones via first bit lines and second latch circuits coupled to said second ones via second bit lines are set with first data and second data, respectively, and

wherein after setting of the first and second latch circuits with said first and said second data, said program operation of said first and said second ones are programmed in parallel bit by bit in response to said first data and said second data set in said first and second latch circuits.

2. A nonvolatile memory according to claim 1,

wherein after said program operation, each of said first ones has one of said first state and said second state according to said first data, and each of said second ones has one of said first state and said second state according to said second data.

3. A nonvolatile memory according to claim 2,

wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a first threshold voltage range and a second threshold range, said first threshold voltage range corresponds to said first state and said second threshold voltage range corresponds to said second state, and

wherein said program operation is to move a threshold voltage of said second ones coupled to said selected word line to one of said first threshold voltage range and said second threshold voltage range according to said second data.

4. A nonvolatile memory according to claim 3,

wherein a higher limit voltage of said first threshold voltage range is lower than a lower limit voltage of said second threshold voltage range.

5. A nonvolatile memory according to claim 4,

wherein said first threshold voltage range indicates an erase state and said second threshold voltage range indicates to a program state.

6. A nonvolatile memory comprising:

a plurality of nonvolatile memory cells;

a controller;

a plurality of bit lines;

a plurality of word lines; and

a latch unit,

wherein each of said nonvolatile memory cells has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges, a first threshold voltage range of said plurality of threshold voltage ranges indicates an erase state and a second threshold voltage range of said plurality of threshold voltage ranges indicates a program state, and has a first terminal, a second terminal and a well region,

wherein each of said word lines couples to said first terminals of corresponding ones of said nonvolatile memory cells,

wherein each of said bit lines couples to said second terminals of corresponding ones of said nonvolatile memory cells in parallel,

wherein each of said nonvolatile memory cells coupled to one word line belongs to an arbitrary one of first ones and second ones,

wherein each of said threshold voltages of nonvolatile memory cells belonging to said first ones is within either said first threshold voltage range or said second threshold voltage range according to stored first data,

wherein each of said threshold voltages of nonvolatile memory cells belonging to said second ones is within said first threshold voltage range,

wherein said well regions of adjacent nonvolatile memory cells coupled to one word line are connected,

wherein said controller carries out a program operation, in response to receiving a first command with a second data,

wherein in said program operation, said controller selects one word line, reads out first data from first ones coupled to selected word line, and sets said first data and said second data to said latch unit,

wherein after setting said first data and said second data to said latch unit in said program operation, said controller carries out supply of a first voltage to said selected word line so that said first ones and second ones are programmed in parallel in response to said first data and said second data set in said latch unit.

7. A nonvolatile memory according to claim 6,

wherein said controller controls, in response to receiving a second command, selection of one word line and supplying of a second voltage to a selected word line for changing each threshold voltage of said first ones and second ones to be within said first threshold voltage range.

8. A nonvolatile memory according to claim 7, wherein said latch unit comprises a plurality of latch circuits,

wherein each of said latch circuits couples to a corresponding bit line,

wherein said controller controls setting of a flag to said latch circuits coupled to memory cells objected to change threshold voltage from said first threshold voltage range to said second threshold voltage range before supplying said first voltage to said selected word line.

9. A nonvolatile memory according to claim 8,

wherein said controller controls changing of threshold voltages of memory cells, threshold voltages which are within said second threshold voltage range, to within an intermediate range between said first threshold voltage range and said second threshold voltage range before supplying said first voltage to said selected word line.