Method and apparatus for evaluating and calibrating a signaling system

• US 6,873,939 B1
• Filed: 02/02/2001
• Issued: 03/29/2005
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): LAU, TUNG S
• Application Number:
  US09/776,550
• Time in Patent Office: 1,516 Days
• Field of Search: 702/189, 370/249, 370/229, 370/421, 370/522, 370/29, 370/110, 714/715, 714/822, 714/52, 714/30, 714/726, 714/736, 714/735, 714/705, 714/727, 714/718, 714/724, 713/500, 713/401, 375/347, 375/238, 375/231, 318/587, 709/252, 327/151, 326/30, 379/27, 365/201, 341/100
• US Class Current: 702/189
• CPC Class Codes: G01R 31/31712 Input or output aspects
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

A method and apparatus for evaluating and calibrating a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. Information obtained from testing may be used to assess the effects of various system parameters, including but not limited to output current, crosstalk cancellation coefficients, and self-equalization coefficients, and system parameters may be adjusted to optimize system performance. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. A digital signaling system comprising:

a transmit circuit, the transmit circuit comprising a transmit data input and a transmit data output, the transmit circuit producing a transmit data output signal at the transmit data output based on a transmit data input signal from the transmit data input when the transmit circuit is operating in a normal mode, the transmit circuit further comprising a transmit repeating pattern generator producing a repeating pattern signal, the transmit circuit producing the transmit data output signal at the transmit data output based on the repeating pattern signal when the transmit circuit is operating in a test mode; and

a receive circuit, the receive circuit operably coupled to the transmit circuit and receiving the transmit data output signal from the transmit circuit at a receive data input, the receive circuit comprising a receive data output, the receive circuit producing a receive data output signal at the receive data output based on the transmit data output signal when the receive circuit is operating in the normal mode, the receive circuit further comprising a receive repeating pattern generator producing the repeating pattern signal, the receive circuit producing a comparison signal based on a comparison dependent on the transmit data output signal and the repeating pattern signal when the receive circuit is operating in the test mode.

2. The digital signaling system of claim 1 wherein the transmit repeating pattern generator comprises a transmit shift register and the receive repeating pattern generator comprises a receive shift register.

3. The digital signaling system of claim 2 wherein a transmit shift register output of the transmit shift register is coupled to a transmit shift register input of the transmit shift register when the transmit circuit is operating in the test mode and a receive shift register output of the receive shift register is coupled to a receive shift register input of the receive shift register when the receive circuit is operating in the test mode.

4. The digital signaling system of claim 2 wherein the transmit circuit further comprises a transmit linear feedback logic gate, wherein a first transmit shift register output of the transmit shift register is coupled to a first transmit linear feedback logic input of the transmit linear feedback logic gate, and wherein second transmit shift register output of the transmit shift register is coupled to a second transmit linear feedback logic input of the transmit linear feedback logic gate, the transmit linear feedback logic gate producing a transmit linear feedback logic gate output signal upon which a transmit shift register input signal at a transmit shift register input of the transmit shift register depends when the transmit circuit is operating in the test mode, and wherein the receive circuit further comprises a receive linear feedback logic gate, wherein a first receive shift register output of the receive shift register is coupled to a first receive linear feedback logic input of the receive linear feedback logic gate, and wherein a second receive linear feedback logic input of the receive linear feedback logic gate, the receive linear feedback logic gate producing a receive linear feedback logic gate output signal upon which a receive shift register input signal at a receive-shift register input of the receive shift register depends when the receive circuit is operating in the test mode.

5. The digital signaling system of claim 1 wherein the transmit repeating pattern generator comprises a transmit linear feedback shift register and the receive repeating pattern generator comprises a receive linear feedback shift register.

6. The digital signaling system of claim 1 wherein the transmit data output signal is capable of representing two bits of information simultaneously over a single conductor.

7. The digital signaling system of claim 1 wherein the transmit data output signal is communicated over a single conductor referenced to a ground voltage.

8. The digital signaling system of claim 1 wherein the transmit data output signal is communicated as a differential signal over two conductors.

9. A method for evaluating a digital signaling system comprising the steps of:

generating a transmit repeating pattern in a transmit circuit;

transmitting the transmit repeating pattern to a receive circuit;

generating a receive repeating pattern in the receive circuit; and

comparing the transmit repeating pattern to the receive repeating pattern to obtain a comparison.

10. The method of claim 9 further comprising the steps of:

adjusting a parameter affecting operation of the transmit circuit based on the comparison.

11. The method of claim 10 wherein the parameter is selected from a group consisting of an output current, a crosstalk cancellation coefficient, and a self-equalization coefficient.

12. The method of claim 9 wherein the step of generating a transmit repeating pattern in a transmit circuit comprises the step of:

utilizing a shift register to generate the transmit repeating pattern.

13. The method of claim 12 wherein the step of utilizing a shift register to generate the transmit repeating pattern comprises the step of:

utilizing a linear feedback shift register to generate the transmit repeating pattern.

14. The method of claim 9 wherein the step of transmitting the transmit repeating pattern to the receive circuit further comprises the step of:

transmitting the transmit repeating pattern as a signal referenced to a ground.

15. The method of claim 9 wherein the step of transmitting the transmit repeating pattern to the receive circuit further comprises the step of:

transmitting the transmit repeating pattern as a differential signal over a pair of conductors.

16. The method of claim 9 wherein the step of transmitting the transmit repeating pattern to the receive circuit further comprises the step of:

transmitting the transmit repeating pattern by encoding two bits of information on a single conductor simultaneously.

17. The method of claim 9 further comprising the step of:

adjusting a receiver characteristic of the receive circuit.

18. The method of claim 17 wherein the receiver characteristic is selected from a group consisting of a receiver circuit timing signal and a voltage reference.

19. The method of claim 17 further comprising the step of:

determining boundary values of the receiver characteristic within which reliable operation of the system is provided.

20. The method of claim 19 further comprising the step of:

adjusting a parameter affecting operation of the transmit circuit based on the boundary values.

21. The method of claim 20 wherein the parameter is selected from a group consisting of an output current, a crosstalk cancellation coefficient, and a self-equalization coefficient.

22. The method of claim 9 wherein the step of generating a receive repeating pattern in the receive circuit comprises the step of:

utilizing a shift register to generate the receive repeating pattern.

23. The method of claim 22 wherein the step of utilizing a shift register to generate the receive repeating pattern comprises the step of:

utilizing a linear feedback shift register to generate the receive repeating pattern.