Flash drive/reader with serial-port controller and flash-memory controller mastering a second RAM-buffer bus parallel to a CPU bus
First Claim
1. A flash-memory peripheral comprising:
- a local central processing unit (CPU) for executing instructions for operating the flash-memory peripheral;
a CPU bus primarily controlled by the local CPU;
a flash-serial buffer bus not primarily controlled by the local CPU;
a RAM buffer for storing flash data for storage by the flash-memory peripheral;
a flash-memory controller for controlling a flash memory that stores the flash data, having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer;
a serial link for connecting the flash-memory peripheral to a personal computer; and
a serial engine for sending and receiving the flash data serially over the serial link, the serial engine having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer;
wherein the flash data is read from the flash memory by the flash-memory controller and sent over the flash-serial buffer bus to the RAM buffer;
wherein the flash data is read from the RAM buffer through the flash-serial buffer bus to the serial engine to be sent serially over the serial link, wherein incoming flash data is written to the RAM buffer through the flash-serial buffer bus from the serial engine, wherein the incoming flash data is read from the RAM buffer through the flash-serial buffer bus to the flash-memory controller and written to the flash memory, whereby the flash-serial buffer bus transfers the flash data and the CPU bus sends commands to the flash-memory controller and to the serial engine.
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Accused Products
Abstract
A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.
89 Citations
20 Claims
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1. A flash-memory peripheral comprising:
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a local central processing unit (CPU) for executing instructions for operating the flash-memory peripheral;
a CPU bus primarily controlled by the local CPU;
a flash-serial buffer bus not primarily controlled by the local CPU;
a RAM buffer for storing flash data for storage by the flash-memory peripheral;
a flash-memory controller for controlling a flash memory that stores the flash data, having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer;
a serial link for connecting the flash-memory peripheral to a personal computer; and
a serial engine for sending and receiving the flash data serially over the serial link, the serial engine having a slave port for coupling to the CPU bus and receiving commands from the local CPU, and having a master port for coupling to the flash-serial buffer bus for transferring flash data to the RAM buffer;
wherein the flash data is read from the flash memory by the flash-memory controller and sent over the flash-serial buffer bus to the RAM buffer;
wherein the flash data is read from the RAM buffer through the flash-serial buffer bus to the serial engine to be sent serially over the serial link, wherein incoming flash data is written to the RAM buffer through the flash-serial buffer bus from the serial engine, wherein the incoming flash data is read from the RAM buffer through the flash-serial buffer bus to the flash-memory controller and written to the flash memory, whereby the flash-serial buffer bus transfers the flash data and the CPU bus sends commands to the flash-memory controller and to the serial engine. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A flash reader comprising:
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a local processor that executed instructions for controlling operation of the flash reader;
a processor bus, mastered by the local processor, for sending commands from the local processor;
a buffer bus, not connected to the local processor, for transferring flash data;
a RAM buffer for storing flash data;
a flash-memory controller for reading flash data from a flash memory in response to commands from the local processor;
a serial engine for sending the flash data as serial data over a serial interface;
a flash slave port, on the flash-memory controller, for connecting the flash-memory controller to the processor bus as a bus-slave device;
a flash master port, on the flash-memory controller, for connecting the flash-memory controller to the buffer bus when the flash-memory controller acts as a bus-master device;
an engine slave port, on the serial engine, for connecting the serial engine to the processor bus as a bus-slave device;
an engine master port, on the serial engine, for connecting the serial engine to the buffer bus when the serial engine acts as the bus-master device;
a first slave port, on the RAM buffer, for connecting the RAM buffer to the processor bus as a bus-slave device; and
a second slave port, on the RAM buffer, for connecting the RAM buffer to the buffer bus as a bus-slave device when the flash-memory controller or the serial engine acts as the bus-master device, whereby the processor bus transfers commands while the buffer bus transfers the flash data bypassing the local processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A flash device comprising:
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processor means for executing controlling instructions;
first bus means for transferring commands from the processor means;
buffer bus means for transferring flash data that by-passes the processor means;
data buffer means, coupled to the buffer bus means as a bus slave, for storing flash data being read by the flash device;
flash-memory controller means, coupled to the first bus means as a bus slave, and coupled to the buffer bus means as a bus master, for controlling a flash memory and for reading flash data from the flash memory; and
serial engine means, coupled to the first bus means as a bus slave, and coupled to the buffer bus means as a bus master, for reading flash data stored by the data buffer means and for serially transmitting the flash data over a serial link;
wherein the flash data is transferred from the flash-memory controller means to the data buffer means over the buffer bus means bypassing the processor means;
wherein the flash data is transferred from the data buffer means to the serial engine means over the buffer bus means bypassing the processor means, whereby transfers of the flash data use the buffer bus means to bypass the processor means. - View Dependent Claims (19, 20)
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Specification