Direct memory access controller system with message-based programming

• US 6,874,054 B2
• Filed: 12/19/2002
• Issued: 03/29/2005
• Est. Priority Date: 12/19/2002
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Design & Manufacturing Corp. (Broadcom, Inc.)
• Inventors: Wood, John Leland, Willie, Daniel Brian, Fortin, Brian Mark, Clayton, Shawn Adam
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US10/324,310
• Publication Number:
  US 20040123013A1
• Time in Patent Office: 831 Days
• Field of Search: 710/100, 710/22, 710/39, 710/40, 710/52, 710/305, 710/28, 710/313, 710/310, 710/240, 709/212, 709/236, 709/203, 712/36, 714/47, 714/799, 714/48, 711/151, 711/158, 345/535, 345/537, 370/463, 370/465, 370/412
• US Class Current: 710/310
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Claims

1. A data transfer system comprising:

a first bus interface;

a second bus interface;

a first-in-first-out memory coupled to the first bus interface and the second bus interface;

a controller coupled to the first-in-first-out memory; and

a message unit coupled to the controller, the message unit being operable to queue a plurality of data transfer request messages from at least the first bus interface, the controller being operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface.

2. The system of claim 1, wherein the controller is operable to calculate error detection codes for data stored in the first-in-first-out memory.

3. The system of claim 1, wherein the controller is operable to calculate cyclic redundancy codes for data stored in the first-in-first-out memory.

4. The system of claim 1, wherein the controller is operable to calculate checksums for data stored in the first-in-first-out memory.

5. The system of claim 1, wherein the controller is operable to send a data transfer response message via the first or second bus interfaces to a client that sent a data transfer request message.

6. The system of claim 1, wherein the first bus interface may receive a data transfer request message from firmware.

7. The system of claim 1, wherein the first bus interface may receive a data transfer request message from a hardware component.

8. The system of claim 1, wherein the first bus interface is coupled to a host computer bus.

9. The system of claim 1, wherein the first bus interface is coupled to a peripheral card interface (PCI) bus.

10. The system of claim 1, wherein the first bus interface is coupled to a peripheral card interface X (PCI-X) bus.

11. The system of claim 1, wherein the second bus interface is coupled to an application specific integrated circuit (ASIC) bus.

12. The system of claim 1, wherein the controller is operable to transfer data from the first bus interface to the first-in-first-out memory using a first clock domain, and transfer data from the second bus interface to the first-in-first-out memory using a second clock domain.

13. The system of claim 1, wherein the controller is operable to simultaneously process data transfers request messages from a plurality of clients.

14. A memory access controller system comprising:

a first bus interface;

a second bus interface;

a memory controller operable to control reads and writes to a plurality of first-in-first-out memory queues; and

a plurality of channels, each channel being operable to process a data transfer request message from the second bus interface, instruct the memory controller to write data from a second bus to a first-in-first-out memory queue associated with the channel, and instruct the memory controller to read data from the first-in-first-out memory queue to send to a first bus.

15. The memory access controller system of claim 14, wherein each channel comprises a master controller, a first bus data controller and a second bus data controller, wherein the master controller is operable to process a data transfer request message from the second bus interface and instruct the first and second bus data controllers to control the memory controller.

16. The memory access controller system of claim 14, wherein each channel has a configurable priority level.

17. The memory access controller system of claim 14, wherein the first bus interface arbitrates between requests from the plurality of channels to access the memory controller.

18. The memory access controller system of claim 14, wherein the second bus interface arbitrates between requests from the plurality of channels to access the memory controller.

19. The memory access controller system of claim 14, wherein the memory controller calculates an error detection code when data is read from a first-in-first-out memory queue.

20. The memory access controller system of claim 19, being operable to store an error detection code seed value related to a data transfer.

21. The memory access controller system of claim 19, being operable to chain error detection code values.

22. The memory access controller system of claim 19, being operable to suppress a context location read operation.

23. The memory access controller system of claim 14, wherein each channel is operable to examine a plurality of data transfer request messages and coalesce data transfers for data transfer request messages that have contiguous source addresses.

24. The memory access controller system of claim 14, being operable to receive and process data transfer request messages from a plurality of clients.

25. The memory access controller system of claim 14, being operable to receive a data transfer request message from a firmware client.

26. The memory access controller system of claim 14, being operable to receive a data transfer request message from a hardware client.

27. The memory access controller system of claim 14, being operable to receive a data transfer request message from a host computer system.

28. A method of transferring data, the method comprising:

receiving a data transfer request message;

queuing the data transfer request message;

reading the data transfer request message;

reading data specified by the data transfer request message from a source memory location and transferring the data to a first-in-first-out memory; and

transferring the data stored in the first-in-first-out memory to a destination memory location specified by the data transfer request message.

29. The method of claim 28, further comprising forming the data transfer request message.

30. The method of claim 28, further comprising forming a data transfer response message.

31. The method of claim 28, further comprising arbitrating access to the first-in-first-out memory among data transfer request messages with different priorities.

32. The method of claim 28, further comprising calculating an error detection code for data stored in the first-in-first-out memory.

33. The method of claim 28, further comprising updating a credit count register.

34. The method of claim 28, further comprising interleaving a plurality of data transfers and performing error detection operations on the interleaved data transfers.

35. The method of claim 28, further comprising suppressing a context location read operation.

36. The method of claim 28, further comprising coalescing multiple data transfers into a single data transfer.