Coordinated recalibration of high bandwidth memories in a multiprocessor computer

• US 6,874,102 B2
• Filed: 03/05/2001
• Issued: 03/29/2005
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: Stratus Technologies Ireland Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Original Assignee: Stratus Technologies Bermuda Ltd. (Stratus Technologies Bermuda Holdings Ltd.)
• Inventors: Doody, John W., Long, Finbarr Denis, McLoughlin, Michael, O'Keefe, Michael James
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): McCarthy, Christopher
• Application Number:
  US09/799,478
• Publication Number:
  US 20020124202A1
• Time in Patent Office: 1,485 Days
• Field of Search: 714/5, 714/11, 714/12
• US Class Current: 714/12
• CPC Class Codes: G06F 11/1691 using a quantum

Abstract

Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.

Claims

1. A method for providing synchronized recalibration of hardware devices in electrical communication with a memory bus in a fault-tolerant computing environment, said method comprising the steps:

(a) providing a computer having a first and second synchronized central processing units (CPUs) and first and second hardware devices having a recalibration procedure, wherein said first hardware device is associated with said first CPU and said second hardware device is associated with said second CPU;

(b) initiating said recalibration procedure in said first and second hardware devices after the passage of a deterministically-computed delay; and

(c) generating a maintenance clock signal with a period substantially equal to the duration between iterations of said recalibration procedures, wherein the maintenance clock signal is used to initiate the deterministically-computed delay of step (b).

2. The method of claim 1, wherein step (b) comprises the steps:

(b-a) changing the state of a reset signal upon the occurrence of a change in said maintenance clock signal; and

(b-b) initiating said recalibration procedure in said first and second hardware devices after the passage of a deterministically-computed delay triggered by the change in state of said reset signal.

3. The method of claim 2, wherein said change in said maintenance clock signal is an edge transition.

4. The method of claim 2 wherein changing the state of the reset signal comprises the step of deasserting the reset signal.

5. The method of claim 2, wherein changing the state of the reset signal comprises the step of asserting the reset signal.

6. A method for providing synchronized recalibration of hardware devices in electrical communication with a memory bus in a fault-tolerant computing environment, said method comprising the steps:

(a) providing a computer having a first and second synchronized central processing units (CPUs) and first and second hardware devices having a recalibration procedure, wherein said first hardware device is associated with said first CPU and said second hardware device is associated with said second CPU;

(b) initiating said recalibration procedure in said first and second hardware devices after the passage of a deterministically-computed delay; and

(c) generating a system clock having a system clock period, wherein said deterministically-computed delay is an integer multiple of said system clock period.

7. A method for providing synchronized recalibration of hardware devices in electrical communication with a memory bus in a fault-tolerant computing environment, said method comprising the steps:

(a) providing a computer having a first and second synchronized central processing units (CPUs) and first and second hardware devices having a recalibration procedure, wherein said first hardware device is a first memory device connected to said first CPU through the memory bus and said second hardware device is a second memory device connected to said second CPU through the memory bust; and

(b) initiating said recalibration procedure in said first and second hardware devices after the passage of a deterministically-computed delay,

wherein step (a) further comprises providing hardware devices that are RAMBUS memory controller hubs (MCH).

8. A method for providing synchronized recalibration of hardware devices in electrical communication with a memory bus in a fault-tolerant computing environment, said method comprising the steps:

(a) providing a computer having a first and second synchronized central processing units (CPUs) and first and second hardware devices having a recalibration procedure, wherein said first hardware device is a first memory device connected to said first CPU through the memory bus and said second hardware device is a second memory device connected to said second CPU through the memory bus; and

(b) initiating said recalibration procedure in said first and second hardware devices after the passage of a deterministically-computed delay,

wherein step (a) further comprises providing hardware devices that are memory repeater hubs (MRH).

9. A fault-tolerant computer with synchronized memory recalibration, comprising:

a first central processing unit (CPU),

a second CPU, in synchronized operation with said first CPU;

a first hardware device, in electrical communication with said first CPU through a memory bus and having a recalibration procedure;

a second hardware device, in electrical communication with said second CPU through a memory bus and having a recalibration procedure, wherein each of said first and second hardware devices is an integrated memory subsystem; and

a synchronizer in electrical communication with said hardware devices, operating to synchronize the execution of the recalibration procedure in said first hardware device with the execution of the recalibration procedure in said second hardware device,

wherein said hardware devices are RAMBUS memory controller hubs (MCH).

10. A fault-tolerant computer with synchronized memory recalibration, comprising:

a first central processing unit (CPU),

a second CPU, in synchronized operation with said first CPU;

a first hardware device, in electrical communication with said first CPU through a memory bus and having a recalibration procedure;

a second hardware device, in electrical communication with said second CPU through a memory bus and having a recalibration procedure, wherein each of said first and second hardware devices is an integrated memory subsystem; and

a synchronizer in electrical communication with said hardware devices, operating to synchronize the execution of the recalibration procedure in said first hardware device with the execution of the recalibration procedure in said second hardware device,

wherein said hardware devices are memory repeater hubs (MRH).

11. A fault-tolerant computer with synchronized memory recalibration, comprising:

a first central processing unit (CPU),

a second CPU, in synchronized operation with said first CPU;

a first hardware device, in electrical communication with said first CPU through a memory bus and having a recalibration procedure;

a second hardware device, in electrical communication with said second CPU through a memory bus and having a recalibration procedure;

a synchronizer in electrical communication with said hardware devices, operating to synchronize the execution of the recalibration procedure in said first hardware device with the execution of the recalibration procedure in said second hardware device; and

a clock generator in electrical communication with said synchronizer, receiving a system clock signal and generating a maintenance clock signal to initiate the recalibration procedure in said hardware devices.

12. A fault-tolerant computer with synchronized memory recalibration, comprising:

a first central processing unit (CPU),

a second CPU, in synchronized operation with said first CPU;

a first hardware device, in electrical communication with said first CPU through a memory bus and having a recalibration procedure;

a second hardware device, in electrical communication with said second CPU through a memory bus and having a recalibration procedure;

a synchronizer in electrical communication with said hardware devices, operating to synchronize the execution of the recalibration procedure in said first hardware device with the execution of the recalibration procedure in said second hardware device; and

a temperature sensor in electrical communication with said synchronizer and thermally connected to first and second hardware devices, measuring the temperature of said hardware devices.

13. A fault-tolerant computer with synchronized memory recalibration, comprising:

a first central processing unit (CPU),

a second CPU, in synchronized operation with said first CPU;

a first hardware device, in electrical communication with said first CPU through a memory bus and having a recalibration procedure;

a second hardware device, in electrical communication with said second CPU through a memory bus and having a recalibration procedure;

a synchronizer in electrical communication with said hardware devices, operating to synchronize the execution of the recalibration procedure in said first hardware device with the execution of the recalibration procedure in said second hardware device; and

a current sensor in electrical communication with said synchronizer and first and second hardware devices, measuring the output current of said hardware devices.