Integrated testing of serializer/deserializer in FPGA

• US 6,874,107 B2
• Filed: 07/24/2001
• Issued: 03/29/2005
• Est. Priority Date: 07/24/2001
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lesea, Austin H.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US09/912,683
• Publication Number:
  US 20030023912A1
• Time in Patent Office: 1,344 Days
• Field of Search: 714/731, 714/738, 714/742, 714724-726, 326/41, 716/4, 716/16, 341100-101
• US Class Current: 714/725
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation

Abstract

A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Claims

1. A field programmable gate array (FPGA) comprising:

input and output data communication connections;

a serializer/deserializer circuit coupled to the input and output data communication connections; and

a logic array programmed to generate a test data pattern coupled to the output data communication connection, the logic array is further programmed to check a data pattern received on the input data communication connection while performing a built in self test operation.

2. The FPGA of claim 1 further comprises a digital clock manager circuit to generate a clock signal couplable to the logic array, wherein the digital clock manager circuit adds noise and jitter in a controlled manner in both programmable jitter amplitude and programmable jitter frequency to the clock signal during the built in self test operation.

3. The FPGA of claim 1 further comprises a digital clock manager circuit to generate clock signals couplable to the logic array, wherein the digital clock manager circuit creates frequency offsets and phase shift phases between the clock signals during test operations.

4. The FPGA of claim 1 wherein the logic array is further programmed to insert cyclical redundancy check characters in the test data pattern.

5. The FPGA of claim 1 further comprising a memory to store data indicating test operation results.

6. A method of testing a high speed interconnect circuit of a field programmable gate array (FPGA) comprising:

generating a test pattern using programmed logic circuitry of the FPGA;

outputting the test pattern on an output connection;

coupling the test pattern to an input connection of the high speed interconnect circuit;

evaluating data received on the input connection using the programmed logic circuitry; and

storing data indicating a result of the evaluation.

7. The method of claim 6 wherein the logic array is programmed to operate as a linear feedback shift register to provide a pseudo random bit stream as the test pattern.

8. The method of claim 6 further comprises adding an error checking character to the test pattern prior to outputting the test pattern on the output connection.

9. The method of claim 8 wherein evaluating the data received included evaluating the error checking character.

10. A test system comprising:

a test circuit; and

a field programmable gate array (FPGA) coupled to the test circuit, wherein the FPGA comprises,

input and output data communication connections coupled together through the test circuit,

a serializer/deserializer (SERDES) circuit coupled to the input and output data communication connections, and

a logic array programmed to generate a test data pattern coupled to the output data communication connection, the logic array is further programmed to check a data pattern received on the input connection while performing a built in self test operation.

11. The test system of claim 10 wherein the FPGA comprises a memory to store data indicative of a result of the check of the received data pattern.

12. The test system of claim 11 wherein the test circuit accesses the FPGA memory to determine an error status of the FPGA.

13. A method of testing a serializer/deserializer (SERDES) circuit of a field programmable gate array (FPGA) comprising:

programming a logic array of the FPGA;

generating a test pattern using the programmed logic array of the FPGA;

outputting the test pattern on an output connection of the SERDES circuit;

externally coupling the test pattern to an input connection of the SERDES circuit;

using the programmed logic array, evaluating data received on the input connection;

storing data indicating a result of the evaluation in a memory circuit of the FPGA; and

re-programming the logic array to perform an end user application.

14. The method of claim 13 wherein the logic array is programmed to comprise a pseudo random bit generator function, or other stress or test pattern.

15. The method of claim 13 further comprises:

generating a clock signal using a digital clock manager (DCM) circuit; and

coupling the clock signal to the SERDES circuit.

16. The method of claim 13 further comprises:

generating transmit and receive clock signals using a digital clock manager (DCM) circuit, wherein the digital clock manager circuit creates frequency offsets, jitter magnitude and jitter frequency and phase shift phases between the transmit and receive clock signals; and

coupling the clock signal to the SERDES circuit.