Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits
First Claim
1. A crossbar device comprising:
- n input lines;
m output lines; and
a plurality of chains of pass transistors, each chain having a plurality of pass transistors, to selectively couple said n input lines to said m output lines, wherein each of the plurality of chains of pass transistors comprises a first and a second pass transistors coupled such that said first pass transistor drives a load consisting essentially of said second pass transistors and interconnect between said first and said second pass transistor;
where n and m are integers.
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Accused Products
Abstract
A crossbar device includes a first set of input lines and a second set of output lines. A plurality of chains of pass transistors are provided to selectively couple the input lines to the output lines in a reduced parasitic capacitive loading manner. Further, memory elements and decoder logic are provided to facilitate control of the selective coupling. Additionally, a low power application of multiple crossbar devices to a reconfigurable circuit block is improved by having each memory element of a crossbar device be provided with a supply voltage higher by a Vth to maintain the input voltage of corresponding output buffers at Vdd. Further, an application of multiple crossbar devices to a reconfigurable circuit block is improved by coupling a control circuitry via a control line to all output buffers of the interconnected crossbar devices to force the output buffers to a known state at power-on.
9 Citations
20 Claims
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1. A crossbar device comprising:
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n input lines;
m output lines; and
a plurality of chains of pass transistors, each chain having a plurality of pass transistors, to selectively couple said n input lines to said m output lines, wherein each of the plurality of chains of pass transistors comprises a first and a second pass transistors coupled such that said first pass transistor drives a load consisting essentially of said second pass transistors and interconnect between said first and said second pass transistor;
where n and m are integers. - View Dependent Claims (2, 3, 4)
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5. A reconfigurable circuit comprising:
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a plurality of crossbar devices coupled to one another, each crossbar device having at least a memory element, and an output buffer electrically associated with said at least a memory element; and
a voltage supply structure coupled to at least one crossbar device designed to supply Vdd to an input to the output buffer and to raise a voltage raised by a threshold over Vdd to said at least a memory element to maintain an input voltage of the output buffer at Vdd. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A reconfigurable circuit comprising:
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a plurality of crossbar devices coupled to one another, each crossbar device having at least an output buffer; and
a power-on circuitry coupled to the crossbar devices to force the output buffers to a same known logic value at power-on, said same known logic value to facilitate reduction of current drain in said reconfigurable circuit by reducing the number of outputs of said plurality of output buffers at different logic values. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification