Three-dimensional memory

• US 6,875,641 B2
• Filed: 09/22/2003
• Issued: 04/05/2005
• Est. Priority Date: 06/27/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/665,697
• Publication Number:
  US 20040062094A1
• Time in Patent Office: 561 Days
• Field of Search: 438/128, 438/130, 438/131, 438/467, 438/600
• US Class Current: 438/128
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

Claims

1. A process for fabricating two memory levels in a memory array comprising:

forming a first conductive layer;

depositing a first semiconductor layer over the first conductive layer, the first semiconductive layer being doped with a first conductivity type dopant;

forming a first antifuse layer over the first semiconductor layer;

depositing a second semiconductor layer doped with a second conductivity type dopant over the first antifuse layer;

in a first etch step, etching the first conductive layer, the first semiconductor layer, the first antifuse layer, and the second semiconductor layer into a plurality of first parallel, spaced-apart rail-stacks;

filling the space between the first rail-stacks with a first insulator;

planarizing the first upper surface of the first rail-stacks and the first insulator;

forming a second conductive layer over the second semiconductor layer;

depositing a third semiconductor layer doped with a second conductivity type dopant over the second conductive layer;

in a second etch step, etching the second conductive layer and the third semiconductor layer into a plurality of second parallel, spaced-apart rail-stacks;

filling the space between the second rail-stacks with a second insulator;

planarizing the second upper surface of the second insulator and the second rail-stacks;

forming a second antifuse layer on the planarized second upper surface;

depositing a fourth semiconductor layer doped with a first conductivity type dopant over the second antifuse layer;

forming a third conductive layer;

in a third etch step, etching the third semiconductor layer and third conductive layer to form third parallel, spaced-apart rail-stacks;

filling the space between the third rail-stacks with a third insulator.

2. The process defined by claim 1, wherein the first, second, third, and fourth semiconductor layers comprise polysilicon layers.

3. The process defined by claim 1, wherein the first conductivity type is P type, and the second conductivity type is N type.

4. The process defined by claim 3, wherein the N type polysilicon layers are doped to a concentration level of N−

, and the P type polysilicon layers are doped to a concentration level of P+.

5. The process defined by claim 1, wherein the first and second antifuse layers comprise silicon dioxide.

6. The process defined by claim 1, wherein the thickness of layers etched in the second and third etch steps is approximately the same.

7. The process defined by claim 1, wherein the first, second, and third conductive layers comprise a silicide.

8. The process defined by claim 7, wherein silicon is deposited on a metal layer to form the silicide.

9. A process for fabricating two memory levels in a memory array comprising:

forming a first conductive layer;

depositing a first semiconductor layer over the first conductive layer, the first semiconductor layer being doped with a first conductivity type dopant;

forming a first antifuse layer over the first semiconductor layer;

depositing a second semiconductor layer doped with a second conductivity type dopant over the first antifuse layer;

etching the first conductive layer, the first semiconductor layer, the first antifuse layer, and the second semiconductor layer into a plurality of first parallel, spaced-apart rail-stacks;

filling the space between the first rail-stacks with a first insulator;

planarizing the first upper surface of the first rail-stacks and the first insulator;

forming a second conductive layer over the second semiconductor layer;

depositing a third semiconductor layer doped with a second conductivity type dopant over the second conductive layer;

depositing a fourth semiconductor layer doped with a first conductivity type dopant over the third semiconductor layer;

etching the second semiconductor layer, second conductive layer, third semiconductor layer and fourth semiconductor layer into a plurality of second parallel, spaced-apart rail-stacks and an etched fourth semiconductor layer;

filling the space between the second rail-stacks and the etched fourth semiconductor layer with a second insulator;

planarizing the second upper surface of the second insulator and the etched fourth semiconductor layer;

forming a second antifuse layer on be planarized second upper surface;

forming a third conductive layer;

etching the third conductive layer and etched fourth semiconductor layer to form third parallel, spaced-apart rail-stacks;

filling the space between the third rail-stacks with a third insulator.

10. The process defined by claim 9, wherein the first, second, third, and fourth semiconductor layers comprise polysilicon layers.