Method of fabricating trench MIS device with graduated gate oxide layer

• US 6,875,657 B2
• Filed: 03/26/2002
• Issued: 04/05/2005
• Est. Priority Date: 08/10/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Terrill, Kyle, Chen, Kuo-In, Darwish, Mohamed N., Lui, Kam Hong, Pattanayak, Deva N., Yue, Christiana, Giles, Frederick P.
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/106,896
• Publication Number:
  US 20030032248A1
• Time in Patent Office: 1,106 Days
• Field of Search: 438/270, 438/268, 438/271, 438/272, 438/273, 438/274, 257/330
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A process for manufacturing a trench MIS device includes depositing a conformal nitride layer in the trench; etching the nitride layer to create an exposed area at the bottom of the trench; and heating the substrate and thereby growing an oxide layer in the exposed area. This process causes the mask layer to “lift off”, creating a “bird'"'"'s beak” structure. This becomes a “transition region”, where the thickness of the oxide layer decreases gradually in a direction away from the exposed area. The method further includes diffusing a dopant into the substrate, the dopant forming a PN junction with a remaining portion of said substrate, and controlling the diffusion such that the PN junction intersects the trench in the transition region. Because the thickness of the oxide layer decreases gradually, the PN junction does not need to be located at a particular point, i.e., there is a margin of error. This improves the manufacturability of the device and enhances its breakdown characteristics.

Claims

1. A method of fabricating an MIS device comprising:

providing a semiconductor substrate;

forming a trench in said substrate;

depositing a nitride layer in said trench;

etching said nitride layer to form an exposed area at a bottom of said trench;

said etching exposing a lateral surface of said nitride layer on each side of said exposed area;

heating the substrate and thereby growing an oxide layer in said exposed area, said oxide layer abutting said lateral surface of said nitride layer on each side of said exposed area;

removing said nitride layer;

forming a relatively thin gate oxide layer on at least a portion of a sidewall of said trench; and

forming a gate in said trench.

4. The method of claim 1 wherein growing an oxide layer comprises causing a portion of said nitride layer to lift oft from a surface of said trench.

5. The method of claim 1 wherein depositing a nitride layer comprises depositing a nitride layer 500 Å

or less thick.

6. The method of claim 1 wherein depositing a nitride layer comprises depositing a nitride layer in the range of 1,500 to 2,000 Å

thick.

7. The method of claim 1 wherein growing an oxide layer comprises creating a transition region wherein a thickness of the oxide layer gradually decreases in a direction away form said exposed area.

8. The method of claim 7 wherein the substrate is of a first conductivity type, the method further comprising diffusing dopant of a second conductivity type into said substrate, said dopant forming a PN junction with a remaining portion of said substrate.

10. The method of claim 1 comprising implanting dopant through a bottom of said trench to form a heavily doped region adjacent said bottom of said trench.

11. The method of claim 1 wherein etching said nitride layer comprises a directional etch.

12. The method of claim 1 wherein etching said nitride layer comprises a directional, dry plasma etch.

13. The method of claim 1 wherein etching said nitride layer comprises a reactive ion etch.

14. The method of claim 1 wherein said etching said nitride layer leaves a remaining section of said nitride layer covering a corner area of said trench.

2. The method of claim 2, wherein forming a gate comprises:

depositing doped polysilicon in said trench; and

etching said doped polysilicon to a level about equal to a surface of said substrate.

3. A method of fabricating an MIS device comprising:

providing a semiconductor substrate;

forming a trench in said substrate;

depositing a nitride layer in said trench;

etching said nitride layer to form an exposed area at a bottom of said trench;

heating the substrate and thereby growing an oxide layer in said exposed area;

removing a portion of said nitride layer;

oxidizing a remaining portion of said nitride layer to form oxidized nitride;

removing said oxidized nitride

forming a relatively thin gate oxide layer on at least a portion of a sidewall of said trench; and

forming a gate in said trench.

9. A method of fabricating an MIS device comprising:

providing a semiconductor substrate of a first conductivity type;

forming a trench in said substrate;

depositing a nitride layer in said trench;

etching said nitride layer to form an exposed area at a bottom of said trench;

heating the substrate and thereby growing an oxide layer in said exposed area, thereby creating a transition region wherein a thickness of the oxide layer gradually decreases in a direction away form said exposed area; and

diffusing dopant of a second conductivity type into said substrate, said dopant forming a PN junction with a remaining portion of said substrate;

wherein diffusing dopant of said second conductivity type comprises controlling the diffusion of said PN junction such that said PN junction intersects the trench in said transition region.