Method of fabricating vertical integrated circuits

• US 6,875,671 B2
• Filed: 11/19/2003
• Issued: 04/05/2005
• Est. Priority Date: 09/12/2001
• Status: Expired due to Fees

• Current Assignee: Reveo, Inc.
• Original Assignee: Reveo, Inc.
• Inventors: Faris, Sadeg M.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/717,219
• Publication Number:
  US 20040201012A1
• Time in Patent Office: 503 Days
• Field of Search: 438/455, 438/456, 438/458, 438/459, 438/977
• US Class Current: 438/455
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.

Claims

1. A method of fabricating a vertically integrated circuit, the method comprising the steps of:

providing a bulk substrate;

selectively creating strong bond regions and weak bond regions on said substrate;

providing a first bonded semiconductor layer vertically supported on said substrate;

creating semiconductor device portions on said first bonded semiconductor layer, said semiconductor device portions corresponding to said weak bond regions;

removing said first semiconductor layer from said bulk substrate; and

bonding said first semiconductor layer to a second semiconductor layer.

2. The method of claim 1 further comprising the step of aligning said first semiconductor layer with said second semiconductor layer having similarly positioned semiconductor device portions.

3. The method of claim 2, wherein said aligning step is mechanical alignment.

4. The method of claim 2, wherein said aligning step is optical alignment.

5. The method of claim 1 further comprising the step of creating semiconductor device portions on said second semiconductor layer.

6. The method of claim 5, wherein said second semiconductor layer has semiconductor device portions on said weak bond regions.

7. The method of claim 1, wherein the ratio of areas of said strong bond regions to said weak bond regions is greater than 1.

8. The method of claim 1, wherein the ratio of bond strengths of said strong bond regions to said weak bond regions is greater than 1.

9. The method of claim 1 further comprising the step of interconnecting said first semiconductor layer with said second semiconductor layer.

10. The method of claim 9, wherein said step of interconnecting is implemented at the edge of said semiconductor layers.

11. The method of claim 10, wherein said step of interconnecting is electrically coupling.

12. The method of claim 10, wherein said step of interconnecting is optically coupling.

13. The method of claim 9, wherein said step of interconnecting is performed vertically through said semiconductor layers.

14. The method of claim 5, further comprising the steps of:

removing said second semiconductor layer from said bulk substrate; and

bonding said second semiconductor layer to said first semiconductor layer.

15. The method of claim 1, further comprising the steps of:

providing an Nth semiconductor layer vertically supported on said bulk substrate, said Nth semiconductor layer having strong bond regions and weak bond regions;

creating semiconductor device portions on said Nth semiconductor layer, said semiconductor device portions corresponding to said weak bond regions;

removing said Nth semiconductor layer from said bulk substrate; and

bonding said Nth semiconductor layer to an (N−

1)th semiconductor layer.

16. The method of claim 15, wherein active semiconductor elements are formed from any two of said N semiconductor layers.

17. The method of claim 1, further comprising the step of:

dicing said bonded semiconductor layers to form one or more dies.

18. The method of claim 17, further comprising the step of:

interconnecting said bonded semiconductor layers after said dicing step.

19. The method of claim 18, further comprising the step of:

forming edge connectors on the boundary of said one or more dies.

20. The method of claim 19 wherein said edge connectors serve as diagnostic conductors to determine health of individual die layers.

21. The method of claim 1, wherein said bulk substrate includes a buried oxide layer.

22. The method of claim 21, wherein said buried oxide layer is formed by ion implantation.