Dual depth trench isolation
First Claim
1. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:
- forming a photoresist material over a silicon substrate;
forming a photoresist pattern from said photoresist material to form a first, second and third level into said photoresist pattern, said first level defining active areas within said silicon substrate, said second level defining an intra-well width, an intra-well depth, a first inter-well width and a first inter-well depth, said third level defining a second inter-well width and a second inter-well depth;
etching said silicon substrate by transferring said photoresist pattern thereto to form an inter-well trench having an overall combined width and depth comprising said first inter-well width, said first inter-well depth, said second inter-well width and said second inter-well depth, said step of etching simultaneously forming intra-well trenches on opposing sides of said inter-well trench;
forming isolation material in said intra-well trenches and said inter-well trench;
forming conductive wells having a common boundary but having opposite conductivity types within said define active areas, said isolation material interposed at said common boundary of said conductive wells.
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Accused Products
Abstract
A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well region.
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Citations
6 Claims
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1. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:
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forming a photoresist material over a silicon substrate;
forming a photoresist pattern from said photoresist material to form a first, second and third level into said photoresist pattern, said first level defining active areas within said silicon substrate, said second level defining an intra-well width, an intra-well depth, a first inter-well width and a first inter-well depth, said third level defining a second inter-well width and a second inter-well depth;
etching said silicon substrate by transferring said photoresist pattern thereto to form an inter-well trench having an overall combined width and depth comprising said first inter-well width, said first inter-well depth, said second inter-well width and said second inter-well depth, said step of etching simultaneously forming intra-well trenches on opposing sides of said inter-well trench;
forming isolation material in said intra-well trenches and said inter-well trench;
forming conductive wells having a common boundary but having opposite conductivity types within said define active areas, said isolation material interposed at said common boundary of said conductive wells. - View Dependent Claims (2, 3, 4)
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5. A process for forming a dual depth trench isolation structure between active devices and conductive well regions of same conductivity type for a complementary metal oxide semiconductor device comprising:
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forming a first inter-well isolation structure having a first isolation trench depth;
forming a second inter-well isolation structure having a second isolation trench depth, said second isolation trench depth combining with said first isolation trench depth to form a dual depth trench containing said dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure, said dual depth trench isolation interposed at a common boundary of an n-well conductive region and a p-well conductive region;
forming a first intra-well isolation structure, said first intra-well isolation structure interposed between a pair of p-channel transistors residing in said n-well region;
forming a second intra-well isolation structure, said second intra-well isolation structure interposed between a pair of n-channel transistors residing in said p-well region;
wherein said second, third, and fourth forming steps are performed simultaneously and said first and second intra-well isolation structures are entrenched at said second isolation trench depth.
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6. A process for forming a set of transistors of complementary conductivity for a semiconductor device comprising:
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forming a pair of p-channel transistors residing in an n-well region and separated by a first intra-well isolation structure;
forming a pair of n-channel transistors residing in a p-well region and separated by a second intra-well isolation structure;
said first intra-well isolation structure and said second intra-well isolation structure are simultaneously entrenched at a first isolation trench depth;
forming an inter-well isolation structure entrenched at a dual trench depth and interposed at a common boundary of said n-well region and a p-well region;
wherein said dual trench depth of said inter-well isolation structure is stepped such that a first step resides above a second step to form said inter-well structure having a first step wider than an underlying second step, said first step being at substantially the same depth as said intra-well isolation structures and said second step being entrenched deeper than said first step.
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Specification