Dual depth trench isolation

• US 6,875,697 B2
• Filed: 08/24/2004
• Issued: 04/05/2005
• Est. Priority Date: 07/13/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Trivedi, Jigish D.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/925,524
• Publication Number:
  US 20050020088A1
• Time in Patent Office: 224 Days
• Field of Search: 438/700, 438/221, 438/248, 438/427, 438/444, 438/695
• US Class Current: 438/700
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well region.

Claims

1. A process for forming trench isolation in a semiconductor memory device, said process comprising the steps of:

forming a photoresist material over a silicon substrate;

forming a photoresist pattern from said photoresist material to form a first, second and third level into said photoresist pattern, said first level defining active areas within said silicon substrate, said second level defining an intra-well width, an intra-well depth, a first inter-well width and a first inter-well depth, said third level defining a second inter-well width and a second inter-well depth;

etching said silicon substrate by transferring said photoresist pattern thereto to form an inter-well trench having an overall combined width and depth comprising said first inter-well width, said first inter-well depth, said second inter-well width and said second inter-well depth, said step of etching simultaneously forming intra-well trenches on opposing sides of said inter-well trench;

forming isolation material in said intra-well trenches and said inter-well trench;

forming conductive wells having a common boundary but having opposite conductivity types within said define active areas, said isolation material interposed at said common boundary of said conductive wells.

2. The process as recited in claim 1, wherein said step of forming a photoresist pattern comprises using gradient photolithography to impose a gradient exposure on said photoresist material.

3. The process as recited in claim 2, wherein said step of using gradient photolithography comprises implementing a gradient exposure by using a gradient mask so that a gradient exposure intensity corresponds to said first, second and third levels.

4. The process as recited in claim 2, wherein said step of forming a photoresist pattern comprises using masks in succession to form said photoresist pattern corresponding to said first, second and third levels.

5. A process for forming a dual depth trench isolation structure between active devices and conductive well regions of same conductivity type for a complementary metal oxide semiconductor device comprising:

forming a first inter-well isolation structure having a first isolation trench depth;

forming a second inter-well isolation structure having a second isolation trench depth, said second isolation trench depth combining with said first isolation trench depth to form a dual depth trench containing said dual depth trench isolation structure comprising said first inter-well isolation structure and said second inter-well isolation structure, said dual depth trench isolation interposed at a common boundary of an n-well conductive region and a p-well conductive region;

forming a first intra-well isolation structure, said first intra-well isolation structure interposed between a pair of p-channel transistors residing in said n-well region;

forming a second intra-well isolation structure, said second intra-well isolation structure interposed between a pair of n-channel transistors residing in said p-well region;

wherein said second, third, and fourth forming steps are performed simultaneously and said first and second intra-well isolation structures are entrenched at said second isolation trench depth.

6. A process for forming a set of transistors of complementary conductivity for a semiconductor device comprising:

forming a pair of p-channel transistors residing in an n-well region and separated by a first intra-well isolation structure;

forming a pair of n-channel transistors residing in a p-well region and separated by a second intra-well isolation structure;

said first intra-well isolation structure and said second intra-well isolation structure are simultaneously entrenched at a first isolation trench depth;

forming an inter-well isolation structure entrenched at a dual trench depth and interposed at a common boundary of said n-well region and a p-well region;

wherein said dual trench depth of said inter-well isolation structure is stepped such that a first step resides above a second step to form said inter-well structure having a first step wider than an underlying second step, said first step being at substantially the same depth as said intra-well isolation structures and said second step being entrenched deeper than said first step.