High voltage N-LDMOS transistors having shallow trench isolation region

• US 6,876,035 B2
• Filed: 05/06/2003
• Issued: 04/05/2005
• Est. Priority Date: 05/06/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Abadeer, Wagdi W., Tonti, William R., Rankin, Jed H., Gauthier, Robert J. Jr., Brown, Jeffrey S.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/249,766
• Publication Number:
  US 20040222488A1
• Time in Patent Office: 700 Days
• Field of Search: 257/510, 257/343, 257/492, 257/493
• US Class Current: 257/343
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

Claims

1. A transistor comprising:

a gate oxide on a substrate;

a gate on said gate oxide;

a channel region in said substrate below said gate;

a source region in said substrate on one side of said channel region;

a drain region in said substrate on an opposite side of said channel region from said source region;

a shallow trench isolation (STI) region in said substrate between said drain region and said channel region, said STI region having a vertical sidewall extending from a bottom of said STI region; and

a drain extension below said STI region, wherein said drain extension is separated from said gate oxide.

2. The transistor in claim 1, wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region.

3. The transistor in claim 1, wherein said STI region is below a portion of said gate.

4. The transistor in claim 1, wherein said drain extension provides a conductive path between said drain region and said channel region around a lower perimeter of said STI region.

5. The transistor in claim 1, wherein said drain region is positioned further from said gate than said source region is positioned from said gate.

6. A transistor comprising:

a gate on a substrate;

a channel region in said substrate below said gate;

a source region in said substrate on one side of said channel region;

a drain region in said substrate on an opposite side of said channel region from said source region;

a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and

a drain extension below said STI region;

wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extension along said bottom of said STI region comprise different dopant implants than said portions of said drain extension along said sides of said STI region.

7. A transistor comprising:

a gate on a substrate;

a channel region in said substrate below said gate;

a source region in said substrate on one side of said channel region;

a drain region in said substrate on an opposite side of said channel region from said source region;

a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and

a drain extension below said STI region;

wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, said vertical sides of said STI region extending from a bottom of said STI region, wherein portions of vertical said drain extension along sides of said STI region extend from said bottom of said STI region to a position partially up said sides of said STI region, wherein said drain extension is separated from gate oxide.

8. A transistor comprising:

a gate oxide on a substrate;

gate on said gate oxide;

a channel region in said substrate below said gate;

a source region ni said substrate on one side of said channel region;

a drain region in said substrate on an opposite side of said channel region from said source region;

a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and

a drain extension below said STI region, wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, and said drain extension is separated from said sate oxide.

9. A transistor in claim 8, wherein said STI region is below a portion of said gate.

10. A transistor in claim 8, wherein said drain extension provides a conductive path between said drain region and said channel region around a lower perimeter of said STI region.

11. A transistor in claim 8, wherein said drain region is positioned further from said gate than said source region is positioned from said gate.

12. A transistor comprising:

a gate oxide on a substrate;

a channel region in said substrate below said gate;

a source region in said substrate on one side of said channel region;

a drain region in said substrate on an opposite side of said channel region from said source region;

a shallow trench isolation (STI) region in said substrate between said drain region and said channel region; and

a drain extension below said STI region, wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI region, wherein portions of said drain extension along said bottom of said STI region comprise different dopant implants than said portions of said drain extension along said sides of said STI region.

wherein portions of said drain extension along sides of said STI region extend from said bottom of said STI region to a position partially up said sides of said STI region.