Ground plane for exposed package

• US 6,876,069 B2
• Filed: 06/16/2003
• Issued: 04/05/2005
• Est. Priority Date: 02/26/2002
• Status: Expired due to Term

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: ST Assembly Test Services Inc.
• Inventors: Punzalan, Jefferey D., Han, Byung Joon, Yee, Jae Hak, Zheng, Zheng, Tan, Hien Boon
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US10/462,264
• Publication Number:
  US 20040070055A1
• Time in Patent Office: 659 Days
• Field of Search: 257/676, 257/691, 257/784, 257/666
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A new design is provided for the design of a leadframe of a semiconductor package. A ground plane is added to the design of the leadframe, the ground frame is located between the leadframe and the die attach paddle over which the semiconductor device is mounted.

Claims

1. An interface for mounting a semiconductor device in a semiconductor package, comprising:

a die attach paddle;

a leadframe; and

a ground plane as a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle.

2. The interface of claim 1, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

3. The interface of claim 1, said ground-plane comprising a square or rectangular geometric shape when viewed in top view.

4. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said around plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

5. The semiconductor device package of claim 4, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires.

6. The semiconductor device package of claim 4, said second conductive interconnects comprising ground wires.

7. The semiconductor device package of claim 4, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

8. The semiconductor device package of claim 4, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

9. An interface for mounting a semiconductor device in a semiconductor package, comprising:

a die attach paddle;

a leadframe; and

a ground plane as a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle.

10. The interface of claim 9, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

11. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

12. The semiconductor device package of claim 11, said second conductive interconnects comprising ground wires.

13. The semiconductor device package of claim 11, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

14. The semiconductor device package of claim 11, said ground plane comprising a square or rectangular geometric shape when viewed in top view.

15. A semiconductor device package, comprising:

a semiconductor device, said semiconductor device being mounted over a die attach paddle after a layer of die attach paste has been deposited over the surface of said die attach paddle;

a leadframe;

a ground plane, forming a physical and thereto connected interface between said die attach paddle and said lead frame, a plane of said ground plane being interposed between a plane of said die attach paddle and a plane of said lead frame, a plane of said ground plane being parallel with a plane of said die attach paddle, a plane of said ground plane further being parallel with a plane of said lead frame, said ground plane comprising separated layers of metal spatially surrounding said die attach paddle;

first conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and the surface of said lead frame, said first conductive interconnects being selected from the group consisting of signal wires and ground wires and power wires;

second conductive interconnects having been provided between points of electrical contact on an active surface of the semiconductor die and said ground plane, said second conductive interconnects comprising ground wires; and

a mold compound overlying said die attach paddle, further enclosing said ground plane, further enclosing said first and second conductive interconnects, further enclosing said lead frame by a measurable amount.

16. The semiconductor device package of claim 15, said physical and thereto connected interface between said die attach paddle and said lead frame comprising metal interconnects in metal strip form, a plane of said metal interconnects intersecting a plane of said die attach paddle under an angle.

17. The semiconductor device package of claim 15, said ground plane comprising a square or rectangular geometric shape when viewed in top view.