Method for accurate output voltage testing

• US 6,876,218 B1
• Filed: 02/14/2003
• Issued: 04/05/2005
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Simmons, Tuyet Ngoc, Lai, Andrew W.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US10/367,385
• Time in Patent Office: 781 Days
• Field of Search: 324/158.1, 324/763, 324/765, 324/73.1, 327/597, 327 62- 67, 714/724, 714/733, 438 14- 18
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer

Abstract

A method for accurate testing of the output voltage of an integrated circuit comprises enabling a differential voltage comparator on the integrated circuit to be tested. One input to the differential comparator is set to a reference voltage, and the other input is coupled to a node to be tested. A current load is injected at the node, and the output of the voltage comparator can be used to determine if the integrated circuit performs within the specifications set by a manufacturer.

Claims

1. A method for testing an integrated circuit comprising:

applying a reference voltage to a first input of a differential comparator located on the integrated circuit;

injecting a current at an I/O pad of the integrated circuit, wherein the I/O pad is coupled to a second input of the differential comparator;

enabling an output buffer, wherein an output of the output buffer is coupled to the I/O pad; and

comparing a voltage level of the first input of the differential comparator with a voltage level of the second input of the differential comparator.

2. The method of claim 1 wherein the voltage level of the first input of the differential comparator corresponds to an I/O standard of the integrated circuit.

3. The method of claim 1 further comprising:

if the voltage level of the first input of the differential comparator is less than the voltage level of the second input of the differential comparator, discarding the integrated circuit.

4. The method of claim 1 further comprising:

if the voltage level of the first input of the differential comparator is greater than the voltage level of the second input of the differential comparator, discarding the integrated circuit.

5. A test configuration for testing an integrated circuit comprising:

a differential comparator located on the integrated circuit, having first and second inputs;

a reference voltage source coupled to the first input of the differential comparator;

a current source coupled to the second input of the differential comparator; and

an output buffer of the integrated circuit coupled to the second input of the differential comparator.

6. The test configuration of claim 5 wherein the differential comparator provides a differential amplifier input of the integrated circuit.

7. The test configuration of claim 5 wherein the current source is located on the integrated circuit.

8. The test configuration of claim 5 further comprising:

automated test equipment coupled to the integrated circuit.

9. The test configuration of claim 8 wherein the reference voltage source is a part of the automated test equipment.

10. The test configuration of claim 8 wherein the current source is a part of the automated test equipment.

11. The test configuration of claim 8 wherein the automated test equipment is coupled to the integrated circuit through a test interface.

12. The test configuration of claim 5 wherein the integrated circuit is a programmable logic device.

13. The test configuration of claim 5 further comprising:

support logic for enabling the output buffer and for retrieving an output of the comparator.

14. The test configuration of claim 13 wherein the support logic comprises a shift register.

15. The test configuration of claim 14 wherein the shift register has two registers at each stage.

16. The test configuration of claim 13 wherein the support logic comprises an AND gate.

17. The test configuration of claim 16 wherein the AND gate is implemented as a chain of multiplexers.

18. The test configuration of claim 13 wherein the support logic is programmed in a programmable logic device.

19. A method for testing a programmable logic device comprising:

enabling a differential amplifier input of an I/O block of the programmable logic device;

enabling an output buffer of the I/O block, the output buffer having an output coupled to a first input of the differential amplifier input;

applying a reference voltage source to a second input of the differential amplifier input; and

injecting a current at the first input of the differential amplifier input.

20. The method of claim 19 wherein the reference voltage source corresponds to an I/O standard of the programmable logic device.

21. The method of claim 19 wherein the differential amplifier input is an HSTL input.