Integrated modulator and demodulator configuration

• US 6,876,319 B2
• Filed: 11/27/2002
• Issued: 04/05/2005
• Est. Priority Date: 09/20/2002
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Chiuchiolo, Paul J. Jr., Ponton, Kent A., Webster, Mark A.
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/306,020
• Publication Number:
  US 20040056785A1
• Time in Patent Office: 860 Days
• Field of Search: 341/144, 341/155, 341/143, 341/61, 375/324
• US Class Current: 341/143
• CPC Class Codes: H03C 3/40 using two signal paths the outputs of which have a predetermined phase difference and at least one output being amplitude-modulated
• CPC Class Codes: H03D 3/006 by sampling the oscillations and further processing the samples, e.g. by computing techniques H03D3/007 takes precedence
• CPC Class Codes: H03H 17/0275 comprising non-recursive filters
• CPC Class Codes: H03H 17/0657 where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
• CPC Class Codes: H03H 2218/04 In-phase and quadrature [I/Q] signals

Abstract

An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate. The digital sign inverter negates selected digital samples according to Weaver modulation.

Claims

1. An integrated demodulator and decimator circuit for processing digital samples of a received signal having a predetermined intermediate frequency (IF) and sampled at a sample rate based on a clock having a frequency that is four times the IF, said integrated demodulator and decimator circuit comprising:

a digital sign inverter that sign inverts selected digital samples according to a predetermined phase-shift pattern and that outputs demodulated digital samples at said sample rate; and

a decimator, comprising a symmetric half-band FIR filter with a plurality of taps including alternate zero and non-zero taps and a center tap, wherein said demodulated digital samples are sequentially shifted through said plurality of taps at said sample rate, and wherein said decimator outputs complex digital values at half said sample rate including real output values based on demodulated digital samples shifted into alternate taps and corresponding imaginary output values based on demodulated digital samples shifted into said center tap.

2. The integrated demodulator and decimator circuit of claim 1, wherein said decimator comprises:

a shift register that sequentially shifts said demodulated digital samples through a plurality of sequential memory positions at said sample rate;

a symmetric half-band FIR filter circuit coupled to alternate memory positions of said shift register corresponding to non-zero taps; and

a select circuit, coupled to said shift register and said filter circuit, that outputs said real output values generated by said filter circuit and imaginary output values based on selected demodulated digital samples shifted into a memory position corresponding to said center tap.

3. The integrated demodulator and decimator circuit of claim 2, wherein said select circuit performs decimation by two by discarding output value sets associated with every other sequential shift through said shift register.

4. The integrated demodulator and decimator circuit of claim 2, wherein said filter circuit comprises:

a plurality of adders coupled to said alternate memory positions corresponding to non-zero taps, each adder adding a pair of symmetrical tap memory positions on either side of said center tap;

a plurality of multipliers, each multiplier for multiplying an output of a corresponding adder with a corresponding one of a plurality of predetermined coefficients; and

an output adder that adds the outputs of the plurality of multipliers for determining said real output values.

5. The integrated demodulator and decimator circuit of claim 1, further comprising a second symmetric half-band FIR filter decimator that receives and decimates by two said complex digital values.

6. The integrated demodulator and decimator circuit of claim 1, wherein said digital sign inverter negates selected digital samples base on Weaver demodulation.

7. The integrated demodulator and decimator circuit of claim 6, wherein said digital sign inverter performs a 2'"'"'s complement operation on every other pair of digital samples.

8. The integrated demodulator and decimator circuit of claim 1, wherein the received signal is based on orthogonal frequency division multiplexing (OFDM) having an IF of approximately 20 megahertz (MHz) and wherein the sample rate is approximately 80 mega samples per second (Msps).

9. An integrated modulator and interpolator circuit for modulating a carrier signal having a predetermined intermediate frequency (IF) with a baseband signal sampled at a sample rate having approximately the same frequency as the IF and interpolated into complex digital samples at twice the sample rate, said integrated modulator and interpolator circuit comprising:

a FIR filter interpolator having a plurality of taps, comprising;

a first polyphase filter including alternate taps of said plurality of taps for receiving and filtering real digital samples of the complex digital sample at the first sample rate;

a second polyphase filter including remaining taps of said plurality of taps for receiving and filtering imaginary digital samples of the complex digital samples at the sample rate; and

a multiplexer coupled to outputs of said first and second polyphase filters for providing interpolated digital samples at four times the sample rate; and

a digital sign inverter that negates selected digital samples of said interpolated digital samples according to a predetermined phase-shift pattern and that outputs modulated digital samples of a modulated signal at the IF.

10. The integrated modulator and interpolator circuit of claim 9, wherein said interpolator comprises a symmetric half-band FIR filter.

11. The integrated modulator and interpolator circuit of claim 10, wherein said first polyphase filter comprises taps with predetermined non-zero coefficients and wherein said second polyphase filter includes a unity center tap and a plurality of zero coefficient taps.

12. The integrated modulator and interpolator circuit of claim 9, wherein said digital sign inverter negates every other pair of digital samples in accordance with Weaver modulation.

13. The integrated modulator and interpolator circuit of claim 9, wherein the IF is 20 MHz and wherein the sample rate is 20 mega samples per second (Msps).

14. A method of demodulating an analog signal having a predetermined intermediate frequency (IF), comprising:

sampling the analog signal based on a sample clock with a frequency of approximately four times the IF to provide digital samples;

negated selected ones of said digital samples according to a predetermined phase-shift pattern to provide demodulated digital samples;

shifting said demodulated digital samples through sequential taps of symmetric half-band FIR filter at a sample rate based on the sample clock, the FIR filter having symmetric alternate zero and non-zero taps on either side of a center tap;

providing, from the FIR filter, imaginary values based on every other digital sample shifted into said center tap;

providing, from the FIR filter, real values by applying predetermined filter coefficients to every other set of digital samples shifted into said non-zero taps; and

decimating by two real and imaginary values output from said FIR filter.

15. The method of claim 14, wherein said sample clock is 80 megahertz (MHz).

16. The method of claim 14, wherein said negating comprises sign inverting every other pair of digital samples according to a sign changing pattern based on Weaver demodulation.

17. The method of claim 16, wherein:

said shifting said demodulated digital samples comprises shifting samples into consecutive memory locations of a shift register; and

wherein said providing real values comprises;

adding symmetric pairs of demodulated digital samples shifted into said non-zero taps to provide a plurality of sum values;

multiplying each sum value by a corresponding one of a plurality of predetermined filter coefficients to provide a plurality of filtered values; and

adding said filtered values together.

18. A method of modulating a carrier signal having a predetermined intermediate frequency (IF) with a digital baseband signal, comprising:

receiving complex digital samples at a predetermined sample rate and providing interpolated complex digital samples at twice said sample rate;

applying real samples of said interpolated complex digital samples to a first polyphase filter including non-zero taps of a plurality of taps of a symmetric half-band FIR filter;

applying imaginary samples of said interpolated complex digital samples to a second polyphase filter including remaining zero taps and a center tap of the plurality of taps of the FIR filter;

selecting digital values at outputs of said first and second polyphase filters to provide interpolated digital values at four times said sample rate; and

sign inverting selected ones of said interpolated digital values according to a predetermined phase-shift pattern to provide modulated digital values at four times said sample rate and modulated at the predetermined IF.

19. The method of claim 18, wherein said receiving a complex digital data stream comprises receiving OFDM samples at a rate of approximately 20 mega samples per second (Msps).

20. The method of claim 18, wherein said symmetric half-band FIR filter has a unity center tap and alternating zero and non-zero coefficient taps in which the center tap and zero coefficient taps are provided within the second polyphase filter.

21. The method of claim 18, wherein said sign inverting comprises digitally negating every other pair of selected digital values in accordance with a Weaver demodulation phase-shift pattern.

22. A baseband processor for a radio frequency (RF) transceiver, the baseband processor comprising:

a transmit processor including an integrated modulator and interpolator, comprising;

a transmit packet kernel that converts raw data into a complex digital sample stream at a predetermined sample rate, said complex digital sample stream including real and imaginary digital samples;

an interpolator that converts said complex digital sample stream into an interpolated complex data stream at twice said sample rate;

a first symmetric half-band FIR filter having a plurality of taps comprising a first polyphase filter including every other tap of said plurality of taps for receiving and filtering real digital samples of said interpolated complex sample stream and a second polyphase filter with remaining taps of said plurality of taps for receiving and filtering imaginary digital samples of said interpolated complex sample stream;

a multiplexer coupled to outputs of said first and second polyphase filters for providing an interpolated digital sample stream at four times said sample rate;

a first digital sign inverter that negates selected digital samples of said interpolated digital sample stream according to a predetermined phase-shift pattern and that outputs a modulated digital sample stream at a predetermined intermediate frequency (IF); and

a digital to analog converter (DAC) that converts said modulated digital sample stream into an analog signal; and

a receive processor including an integrated demodulator and decimator, said comprising;

an analog to digital converter (ADC) that samples a received IF signal at four times said sample rate and that outputs a digital sample stream;

a second digital sign inverter that receives said digital sample stream from said ADC, that negates selected digital samples according to a predetermined phase-shift pattern and that outputs a demodulated digital sample stream;

a second symmetric half-band FIR filter with a plurality of taps including a center tap that receives said demodulated digital sample stream and outputs a stream of complex digital values at half said sample rate, said stream of complex digital values including real output values based on digital samples shifted into alternate non-zero taps on either side of said center tap and corresponding imaginary output values based on digital samples shifted into said center tap; and

a second decimator that receives and decimates by two said stream of complex digital values from said first decimator.

23. The baseband processor of claim 22, wherein said transmit packet kernel converts data according to orthogonal frequency division multiplexing (OFDM).

24. The baseband processor of claim 22, wherein said IF is 20 MHz and wherein said predetermined sample rate is 80 Msps.

25. The baseband processor of claim 22, wherein said first and second digital sign inverters negate selected digital samples based on Weaver demodulation and Weaver modulation, respectively.