Unified SRAM cache system for an embedded DRAM system having a micro-cell architecture

• US 6,876,557 B2
• Filed: 06/12/2001
• Issued: 04/05/2005
• Est. Priority Date: 06/12/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Joshi, Rajiv V.
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/879,653
• Publication Number:
  US 20020188797A1
• Time in Patent Office: 1,393 Days
• Field of Search: 365/49, 365/225.7, 365/189.07, 365/200, 365/207
• US Class Current: 365/49.1
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure

Abstract

A unified SRAM cache system is provided incorporated several SRAM macros of an embedded DRAM (eDRAM) system and their functions. Each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified SRAM cache system. The incorporated SRAM macros share a single set of support circuits, such as row decoders, bank decoders, sense amplifiers, wordline drivers, bank pre-decoders, row pre-decoders, I/O drivers, multiplexer switch circuits, and data buses, without compromising the performance of the eDRAM system.

Claims

1. A unified SRAM cache system for storing SRAM cache data and non-SRAM cache data for an embedded DRAM (eDRAM) system, the unified SRAM cache system comprising:

an SRAM cache for storing SRAM cache data; and

at least one non-SRAM cache for storing non-SRAM cache data, wherein the SRAM cache and the at least one non-SRAM cache are configured for sharing one of a set of bitlines and a set of wordlines.

2. The system according to claim 1, wherein the SRAM cache and the at least one non-SRAM cache share at least one external circuit for one of reading and writing data from and to the SRAM cache and the at least one non-SRAM cache.

3. The system according to claim 2, wherein the at least one external circuit is selected from the group consisting of a sense amplifier, a row decoder, a bank decoder, a wordline driver, a bank pre-decoder, a row pre-decoder, an I/O driver, a multiplexer switch circuit, and a data bus.

4. The system according to claim 1, wherein the at least one non-SRAM cache is selected from the group consisting of a TAG block cache, a test program code cache, and a fuse information cache having a column fuse information cache and a row fuse information cache.

5. The system according to claim 3, wherein the multiplexer switch circuit is connected to the sense amplifier circuit for one of reading data stored within the SRAM cache and the at least one non-SRAM cache, and writing data to the SRAM cache and the at least one non-SRAM cache.

6. The system according to claim 3, wherein the multiplexer switch circuit is connected to at least two buses and includes at least two switches for switching between the at least two buses, wherein the at least two switches are controlled by at least two control signals.

7. The system according to claim 6, wherein a first control signal of the at least two control signals includes a fuse read control signal for controlling a first switch of the at least two switches for reading fuse data stored within the at least one non-SRAM cache, and wherein a second control signal of the at least two control signals includes a cache read control signal for controlling a second switch of the at least two switches for reading data stored within the SRAM cache.

8. The system according to claim 6, wherein a first control signal of the at least two control signals includes a fuse write control signal for controlling a first switch of the at least two switches for writing fuse data to the at least one non-SRAM cache, and wherein a second control signal of the at least two control signals includes a cache write control signal for controlling one of a second and a third switch of the at least two switches for one of writing data to the SRAM cache and reading fuse data stored within the at least one non-SRAM cache.

9. The system according to claim 1, wherein the SRAM cache is configured for sharing the set of wordlines with a TAG block cache of the at least one non-SRAM cache.

10. The system according to claim 1, wherein the SRAM cache is configured for sharing the set of bitlines with a fuse information cache of the at least one non-SRAM cache.

11. The system according to claim 10, wherein the fuse information cache is configured for allocating redundant elements during a test mode, for storing fuse information during a redundancy test, and for being accessible by the eDRAM system for selecting available redundant elements as indicated by the stored fuse information to replace defective elements.

12. The system according to claim 1, wherein the SRAM cache is configured for sharing the set of bitlines with a test program code cache of the at least one non-SRAM cache.

13. The system according to claim 1, wherein the SRAM cache and the at least one non-SRAM cache form one of a single-port and a dual-port unified cache memory.

22. The system according to claim 1, wherein the SRAM cache is configured for sharing the set of bitlines with a fuse information cache of the at least one non-SRAM cache.

23. The system according to claim 22, wherein the fuse information cache is configured for allocating redundant elements during a test mode, for storing fuse information during a redundancy test, and for being accessible by the eDRAM system for selecting available redundant elements as indicated by the stored fuse information to replace defective elements.

14. A unified SRAM cache system for storing SRAM cache data and non-SRAM cache data for an embedded DRAM (eDRAM) system, the unified SRAM cache system comprising:

an SRAM cache for storing SRAM cache data; and

at least one non-SRAM cache for storing non-SRAM cache data, wherein the SRAM cache and the at least one non-SRAM cache are configured for sharing at least one external circuit for one of reading and writing data from and to the SRAM cache and the at least one non-SRAM cache,

wherein the SRAM cache and the at least one non-SRAM cache share one of a set of bitlines and a set of wordlines.

15. The system according to claim 14, wherein the at least one external circuit is selected from the group consisting of a sense amplifier, a row decoder, a bank decoder, a wordline driver, a bank pre-decoder, a row pre-decoder, an I/O driver, a multiplexer switch circuit, and a data bus.

16. The system according to claim 14, wherein the at least one non-SRAM cache is selected from the group consisting of a TAG block cache, a test program code cache, and a fuse information cache having a column fuse information cache and a row fuse information cache.

17. The system according to claim 15, wherein the multiplexer switch circuit is connected to the sense amplifier circuit for one of reading data stored within the SRAM cache and the at least one non-SRAM cache, and writing data to the SRAM cache and the at least one non-SRAM cache.

18. The system according to claim 15, wherein the multiplexer switch circuit is connected to at least two buses and includes at least two switches for switching between the at least two buses, wherein the at least two switches are controlled by at least two control signals.

19. The system according to claim 18, wherein a first control signal of the at least two control signals includes a fuse read control signal for controlling a first switch of the at least two switches for reading fuse data stored within the at least one non-S RAM cache, and wherein a second control signal of the at least two control signals includes a cache read control signal for controlling a second switch of the at least two switches for reading data stored within the SRAM cache.

20. The system according to claim 18, wherein a first control signal of the at least two control signals includes a fuse write control signal for controlling a first switch of the at least two switches for writing fuse data to the at least one non-SRAM cache, and wherein a second control signal of the at least two control signals includes a cache write control signal for controlling one of a second and a third switch of the at least two switches for one of writing data to the SRAM cache and reading fuse data stored within the at least one non-SRAM cache.

21. The system according to claim 14, wherein the SRAM cache is configured for sharing the set of wordlines with a TAG block cache of the at least one non-SRAIVI cache.

24. The system according to claim 14, wherein the SRAM cache and the at least one non-SRAM cache form one of a single-port and a dual-port unified cache memory.

25. The system according to claim 14, wherein the SRAM cache is configured for sharing the set of bitlines with a test program code cache of the at least one non-SRAM cache.

26. A unified SRAM cache system for storing SRAM cache data and non-SRA1S4 cache data for an embedded DRAM (eDRAM) system, the unified SRAM cache system comprising:

an SRAM cache for storing SRAM cache data; and

at least one non-SRAM cache for storing non-SRAM cache data, wherein the SRAM cache and the at least one non-SRAM cache form one of a single-port and a dual-port unified cache memory,

wherein the SRAM cache and the at least one non-SRAM cache share one of a set of bitlines and a set of wordlines.

27. The system according to claim 26, wherein the at least one non-SRAM cache is selected from the group consisting of a TAG block cache, a test program code cache, and a fuse information cache having a column fuse information cache and a row fuse information cache.

28. The system according to claim 26 wherein the SRAM cache is configured for sharing the set of wordlines with a TAG block cache of the at least one non-SRAM cache.

29. The system according to claim 26, wherein the SRAM cache is configured for sharing the set of bitlines with a fuse information cache of the at least one non-SRAM cache.

30. The system according to claim 27, wherein the fuse information cache is configured for allocating redundant elements during a test mode, for storing fuse information during a redundancy test, and for being accessible by the eDRAM system for selecting available redundant elements as indicated by the stored fuse information to replace defective elements.

31. The system according to claim 26, wherein the SRAM cache and the at least one non-SRAM cache are configured for sharing at least one external circuit for one of reading and writing data from and to the SRAM cache and the at least one non-SRAM cache.

32. The system according to claim 31, wherein the at least one external circuit is selected from the group consisting of a sense amplifier, a row decoder, a bank decoder, a wordline driver, a bank pre-decoder, a row pre-decoder, an I/O driver, a multiplexer switch circuit, and a data bus.

33. The system according to claim 32, wherein the multiplexer switch circuit is connected to the sense amplifier circuit for one of reading data stored within the SRAM cache and the at least one non-SRAM cache, and writing data to the SRAM cache and the at least one non-SRAM cache.

34. The system according to claim 32, wherein the multiplexer switch circuit is connected to at least two buses and includes at least two switches for switching between the at least two buses, wherein the at least two switches are controlled by at least two control signals.

35. The system according to claim 34, wherein a first control signal of the at least two control signals includes a fuse read control signal for controlling a first switch of the at least two switches for reading fuse data stored within the at least one non-SRAM cache, and wherein a second control signal of the at least two control signals includes a cache read control signal for controlling a second switch of the at least two switches for reading data stored within the SRAM cache.

36. The system according to claim 34, wherein a first control signal of the at least two control signals includes a fuse write control signal for controlling a first switch of the at least two switches for writing fuse data to the at least one non-SRAJVJ cache, and wherein a second control signal of the at least two control signals includes a cache write control signal for controlling one of a second and a third switch of the at least two switches for one of writing data to the SRAM cache and reading fuse data stored within the at least one non-SRAM cache.

37. The system according to claim 26, wherein the SRAM cache is configured for sharing the set of bitlines with a test program code cache of the at least one non-SRAM cache.

38. A method of controlling operation of a unified SRAIVI cache system configured for storing SRAM cache data within an SRAM cache and non-SRAM cache data within at least one non-SRAM cache, the method comprising the steps of:

activating a wordline of a set of wordlines during a first time period to access the SRAM cache; and

activating the wordline of the set of wordlines during a second time period to access the at least one non-SRAM cache, wherein the first time period and the second time period do not overlap.

39. The method according to claim 38, further comprising the step of activating another wordline of the set of wordlines during the first time period to access one of a fuse information cache and a test program code cache of the at least one non-SRAM cache.

40. The method according to claim 38, wherein the step of activating the wordline of the set of wordlines during the second time period to access the at least one non-SRAM cache includes the step of activating the wordline of the set of wordlines during the second time period to access a TAG block cache of the at least one non-SRAM cache.

41. The method according to claim 38, further comprising the step of activating a bitline of a set of bitlines during a third time period to access one of the SRAM cache and a first or second non-SRAM cache of the at least one non-SRAM cache.

42. The method according to claim 41, further comprising the step of activating another bitline of the set of bitlines during the third time period to access a TAG block cache of the at least one non-SRAM cache.