Apparatus and method for power ramp up of wireless modem transmitter

• US 6,876,697 B2
• Filed: 12/12/2000
• Issued: 04/05/2005
• Est. Priority Date: 12/12/2000
• Status: Expired due to Fees

• Current Assignee: Sierra Wireless Incorporated
• Original Assignee: Sierra Wireless Incorporated
• Inventors: Murru, Enrico, Peters, Ken
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): TRAN, KHANH C
• Application Number:
  US09/735,421
• Publication Number:
  US 20020071482A1
• Time in Patent Office: 1,575 Days
• Field of Search: 375/222, 375/285, 375296-297, 375/312, 375/298, 332/103, 332/123, 332/159, 455/127.1, 455/114.3, 455/114.2, 455/115.1, 455/115.2, 455/115.3, 455/127.2, 455/127.3, 455/127.4, 330/2, 330/127, 330/133, 330/135, 330/141
• US Class Current: 375/222
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

A transmitter of a wireless modem may be ramped up with quicker ramp up times and better splatter control by using software controllable ramp up techniques. A digital data signal source sends data to digital-to-analog converters used to generate a ramp with the desired duration and shape for maximum gain with minimum splatter. A transmitter digital-to-analog converter is sent constant I/Q data to bias the input of the I/Q modulator to maximum gain when combined with a direct current voltage. A controller digital-to-analog converter is sent incremented ramp data to shape the ramp and provide maximum gain at the output of the I/Q modulator.

Claims

1. A wireless modem, comprising:

a direct current (DC) bias voltage;

a constant amplitude waveform source to provide a constant amplitude waveform

a variable amplitude waveform source to provide a first variable amplitude waveform and a second variable amplitude waveform;

an In-phase/Quadrature (I/Q) modulator including an input, a gain control and an output, the input of the I/Q modulator being coupled in common with each of the constant amplitude waveform and the DC bias voltage, the gain control of the I/Q modulator coupled with the first variable amplitude waveform, wherein the first variable amplitude waveform provides a first control voltage to bias the output of the I/Q modulator;

a power amplifier (PA) including an input, a gain control and an output, the input of the PA coupled with the output of the I/Q modulator, the gain control of the PA coupled with the second variable amplitude waveform, wherein the second variable amplitude waveform provides a second control voltage to bias the output of the PA; and

a transmitting antenna coupled with the output of the PA,

wherein the constant amplitude waveform source is configured to provide the constant amplitude waveform at device power-up to thereby bias said I/Q modulator to maximum gain, and wherein the variable amplitude waveform source is configured to provide a ramp-up waveform at device start-up to thereby reach a saturation region of the power amplifier.

2. The wireless modem as recited in claim 1, further comprising:

a digital data signal source including a first output to provide a preselected constant digital data and a second output to provide a ramp-up data;

a transmitter digital-to-analog converter (TX_DAC) including an first input, and an output, the input of the TX_DAC being coupled with the first output of the digital data signal source for application of the constant digital data packet, the output of the TX_DAC to provide the constant amplitude waveform;

a controller digital-to-analog converter (CT_DAC) including an input, a first output and a second output, the input of the CTL_DAC being coupled with the second output of the digital data signal source, the first output of the CTL_DAC to provide the first variable amplitude waveform to determine an I/Q modulator gain and the second output of the CTL_DAC to provide the second variable amplitude waveform to determine a power amplifier gain;

a smoothing capacitor coupled with the first output of the CTL_DAC.

3. The wireless modem as recited in claim 2, wherein the preselected constant digital data packet comprises a I/Q data.

4. The wireless modem as recited in claim 2, wherein the digital data signal source further comprises a digital signal processor.

5. The wireless modem as recited in claim 2, wherein the TX_DAC comprises a MAX518Q digital-to-analog converter commercially available by Maxim.

6. The wireless modem as recited in claim 2, wherein the CTL_DAC comprises a TLV5627 digital-to-analog converter commercially available by Texas Instruments.

7. The wireless modem as recited in claim 2, wherein the smoothing capacitor comprises a 330 pF capacitor.

8. A method for ramping up the transmitter power of a wireless modem, the method comprising the steps of:

turning on a power amp (PA) to a desired output;

sending a start data to a modulator to provide a maximum modulator gain;

reading a calibrated ramp target start-up data;

subtracting a first subtraction value from the calibrated ramp target start-up value to provide a ramp start-up data;

sending the calibrated ramp target start-up data to a control digital-to-analog converter (CTL_DAC) to provide a ramp data;

waiting a first CTL_DAC settling time to provide for the output of the CTL_DAC to settle;

incrementing the ramp data to provide a saturation region of the PA; and

ramping up a value of a transmitter automatic gain control (TX_AGC).

9. The method as recited in claim 8, wherein turning on a PA comprises sending PWRCTL data to a PA PWRCTL line.

10. The method as recited in claim 8, wherein the desired output is +30dBm.

11. The method as recited in claim 8, wherein turning on the PA further comprises waiting a PA settling time for the PA output to settle.

12. The method as recited in claim 11, wherein the PA settling time is 15, uS.

13. The method as recited in claim 8, wherein the start data is an I/Q data.

14. The method as recited in claim 13, wherein the I/Q data is constant.

15. The method as recited in claim 8, wherein the calibrated ramp target start-up data is 182.

16. The method as recited in claim 8, wherein the first subtraction value is 24.

17. The method as recited in claim 8, wherein the first CTL_DAC settling time is 2, μ

S.

18. The method as recited in claim 8;

wherein incrementing the ramp data comprises the steps of;

incrementing a value of the ramp data by an increment for an incremental number of times;

writing the value of the ramp data to the CTL_DAC; and

waiting an incremental settling time.

19. The method as recited in claim 18, wherein the increment is 3.

20. The method as recited in claim 18, wherein the incremental number of times is 8.

21. The method as recited in claim 18, wherein the incremental settling time is 1 μ

S.

22. The method as recited in claim 8, wherein ramping up a value of a transmitter automatic gain control (TX_AGC) comprises the steps of:

reading a transmitter power (TX_PWR) data;

subtract a second subtraction value from the TX_PWR data to provide a start point;

sending the start point to the CTL_DAC to provide a TX_AGC ramp data;

waiting a start point settling time;

incrementing the TX_AGC ramp data by an second increment for a second incremental number of times;

writing the TX_AGC ramp data to the CTL_DAC after each increment; and

waiting a second incremental settling time after each write.

23. The method as recited in claim 22, wherein the TX_PWR data is 255.

24. The method as recited in claim 22, wherein the second subtraction value is 48.

25. The method as recited in claim 22, wherein the start point settling time is 50 nS.

26. The method as recited in claim 22, wherein the second increment is 16.

27. The method as recited in claim 22, wherein the second incremental number of times is 3.

28. The method as recited in claim 22, wherein the second incremental settling time is 50 nS.

29. A method for ramping up an output power of a transmitter, comprising the steps of:

turning on a power amplifier (PA);

stabilizing an output of the PA;

sending constant In-phase/Quadrature data to a transmitter digital-to-analog converter (TX_DAC);

combining a TX_DAC output with a direct current voltage at an I/Q modulator input to bias the I/Q modulator to a maximum gain;

sending a ramp-up data from a digital signal processor (DSP) to a controller digital-to-analog converter (CTL_DAC) to provide a first output voltage which determines the PA gain and a second output voltage which determines the I/Q modulator gain;

ramping up a value of a transmitter automatic gain control (TX_AGC) data; and

terminating sending the constant I/Q data to the TX_DAC whereby successive data packets may then be sent.

30. The method as recited in claim 29, wherein turning on the PA comprises sending PWRCTL data to a PA PWRCTL line to provide a desired output level.

31. The method as recited in claim 30, wherein the desired output level is +30 dBm.

32. The method as recited in claim 29, wherein stabilizing the output of the PA comprises waiting a PA settling time.

33. The method as recited in claim 32, wherein the PA settling time is 15, μ

S.

34. The method as recited in claim 29, wherein the step of ramping up the value of the TX_AGC data comprising the steps of:

a) reading a calibrated value of a data to be sent to the TX_AGC;

b) subtracting a first subtraction value from the calibrated value to provide a start value, whereby the start value represents a start of the transmitter ramp-up curve;

c) writing the start value to the CTL_DAC;

d) waiting an initial settling time to provide for an CTL_DAC output to settle;

e) incrementing the start value by adding the start value to a first incremental value to provide an incremented start value;

f) writing the incremented start value to the CTL_DAC, wherein the incremented start value is now designated as the start value;

g) waiting a first settling time;

h) determining a number of incremental steps;

i) repeating (e) through (h) until the number of incremental steps equals a first incremental end value;

j) reading a TX_PWR data to provide a TX_AGC value required to keep the PA in constant saturation;

k) subtracting a second subtraction value from the TX_AGC value to provide a TX_AGC ramp data;

l) writing the TX_AGC ramp data to the CTL_DAC;

m) waiting a second settling time;

n) incrementing the TX_AGC ramp data by adding the TX_AGC ramp data to a second incremental value to provide an incremented TX_AGC ramp data, wherein the incremented TX_AGC ramp data is now designated as the TX_AGC ramp data;

o) writing the TX_AGC ramp data to the CTI,_DAC;

p) waiting a third settling time;

q) determining a second number of incremental steps;

r) repeating (n) through (q) until the second number of incremental steps equals a second incremental end value.

35. The method as recited in claim 34, wherein the calibrated value of the data to be sent to the TX_AGC is an 8-bit value corresponding to a decimal value selected from the group of decimals consisting of 0 through 255, whereby the decimal value is the target value for the TX_AGC and represents an end point of the transmitter ramp-up curve.

36. The method as recited in claim 35, wherein the decimal value is 182.

37. The method as recited in claim 34, wherein the first subtraction value is 24.

38. The method as recited in claim 34, wherein the initial settling time is 2 μ

S.

39. The method as recited in claim 34, wherein the first incremental value is 3.

40. The method as recited in claim 34, wherein the first settling time is 1 μ

S.

41. The method as recited in claim 34, wherein the first incremental end value is 8.

42. The method as recited in claim 34, wherein the TX_PWR value is 255.

43. The method as recited in claim 34, wherein the second subtraction value is 48.

44. The method as recited in claim 34, wherein the second settling time is 50 nS.

45. The method as recited in claim 34, wherein the second incremental value is 16.

46. The method as recited in claim 34, wherein the third settling time is 50 nS.

47. The method as recited in claim 34, wherein the second incremental end value is 3.