Dynamic memory allocation between inbound and outbound buffers in a protocol handler

• US 6,877,048 B2
• Filed: 03/12/2002
• Issued: 04/05/2005
• Est. Priority Date: 03/12/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Schuh, Brian J., Bunce, Robert M., Bilak, Mark R., Parker, Steven C.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Chen, Alan S
• Application Number:
  US10/063,018
• Publication Number:
  US 20030177293A1
• Time in Patent Office: 1,120 Days
• Field of Search: 710/2, 710/5, 710/17, 710/18, 710/30, 710/39, 710 52- 57, 712/225, 711/100, 711/147
• US Class Current: 710/52
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Claims

1. An apparatus for processing data packets comprising:

a first memory buffer capable of receiving incoming data packets;

circuitry capable of generating outgoing data packets from the received incoming data packets or from a host system interface;

a second memory buffer capable of transmitting the generated outgoing data packets;

circuitry capable of dynamically sharing memory from the first memory buffer with the second memory buffer, or from the second memory buffer with the first memory buffer;

wherein said first memory buffer and said second memory buffer each is divided into blocks and said blocks are sized to be smaller than a maximum frame size of the data packet to be processed, and said blocks are managed as one of a free list or as a linked list of blocks.

2. The apparatus of claim 1, further comprising an interprocessor communication path for allowing equal access to said first memory buffer and said second memory buffer.

3. An apparatus for processing data packets comprising:

a first memory buffer capable of receiving incoming data packets;

circuitry capable of generating outgoing data packets from the received incoming data packets or from a host astern interface;

a second memory buffer capable of transmitting the generated outgoing data packets;

circuitry capable of dynamically sharing memory from the first memory buffer with the second memory buffer, or from the second memory buffer with the first memory buffer; and

a processor thread for managing said blocks and for determining an amount of free space available in said first memory buffer and said second memory buffer,

wherein said first memory buffer and said second memory buffer each is divided into blocks and said blocks are sized to be smaller than a maximum frame size of the data racket to be processed.

4. An apparatus for processing data packets comprising:

a first memory buffer capable of receiving incoming data packets;

circuitry capable of generating outgoing data packets from the received incoming data packets or from a host system interface;

a second memory buffer capable of transmitting the generated outgoing data packets;

circuitry capable of dynamically sharing memory from the first memory buffer with the second memory buffer, or from the second memory buffer with the first memory buffer;

an inbound processor, with logic, associated with said first memory buffer, wherein said first memory buffer is dedicated to said inbound processor; and

an outbound processor, with logic, associated with said second memory buffer, wherein said second memory buffer is dedicated to said outbound processor.

5. The apparatus of claim 4, wherein said first memory buffer and said second memory buffer each is divided into blocks and said blocks are sized to be smaller than a maximum frame size of the data packet to be processed.

6. A method of processing data packets employing dynamic memory allocation between inbound and outbound memory buffers, said method comprising the steps of:

receiving incoming data packets via a first memory buffer;

generating outgoing data packets from said received data packets or from a host system interface;

transmitting said outgoing data packets generated via a second memory buffer;

dynamically allocating memory between said first memory buffer and said second memory buffer for optimally receiving said incoming data packets and for storing and transmitting said outgoing data packets;

providing an inbound processor, with logic, wherein said first memory buffer is dedicated to said inbound processor;

providing an outbound processor, with logic, wherein said second memory buffer is dedicated to said outbound processor; and

wherein the memory in said inbound memory buffer and said outbound memory buffer is sharable.

7. The method of claim 6, further comprising the steps of dividing said inbound memory buffer and said outbound memory buffer into blocks and said blocks are sized to be smaller than a maximum frame size of the data packet to be processed.

8. The method of claim 7, further comprising the step of managing said blocks as one of a free list or as a linked list of blocks.

9. The method of claim 7, further comprising the steps of managing said blocks using a processor thread for determining an amount of free space available in said inbound memory buffer and in said outbound memory buffer.

10. The method of claim 6, further comprising the step of allowing equal access to said inbound memory buffer and said outbound memory buffer using an interprocessor communication path.

11. The method of claim 6, further comprising the step of throttling data frame reception rate in the event insufficient memory exists in said inbound memory buffer or said outbound memory buffer.