Central processing unit (CPU) accessing an extended register set in an extended register mode
First Claim
1. A central processing unit (CPU) comprising:
- a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;
wherein the number of standard registers is less than or equal to a number of general purpose registers defined by a CPU architecture, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture.
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Accused Products
Abstract
A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended register set. The standard register set includes multiple standard registers, and the extended register set include multiple extended registers. The execution core fetches and executes instructions, and receives a signal indicating an operating mode of the CPU. The execution core responds to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register. The standard registers may be general purpose registers of a CPU architecture associated with the instruction. The number of extended registers may be greater than the number of general purpose registers defined by the CPU architecture. In this case, the additional register identification information in the prefix portion is needed to identify a selected one of the extended registers. A width of the extended registers may also be greater than a width of the standard registers. In this case, the prefix portion may also include an indication that the entire contents of the least one extended register is to be accessed. In this way, instruction operand sizes may selectively be increased when the CPU is operating in the extended register mode. A computer system including the CPU is also described.
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Citations
39 Claims
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1. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;
wherein the number of standard registers is less than or equal to a number of general purpose registers defined by a CPU architecture, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;
wherein the instruction absent the extended register prefix byte includes register identification information sufficient to identify a selected one of the standard registers, and wherein the extended register prefix byte includes additional register identification information needed to identify a selected one of the extended registers. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of general purpose registers defined by a CPU architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture, and wherein a width of the extended registers is greater than a width of the general purpose registers defined by the CPU architecture; and
an execution core coupled to the register file and to receive the signal indicating the operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing the entire contents of at least one extended register if;
(i) the signal indicates the CPU is operating in an extended register mode, (ii) the instruction includes a prefix portion including information needed to access the at least one extended register, and (iii) the prefix portion includes an indication that the entire contents of the least one extended register is to be accessed. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;
wherein the instruction absent the prefix portion includes register identification information sufficient to identify a selected one of the standard registers, and wherein the prefix portion of the instruction includes additional register identification information needed to identify a selected one of the extended registers. - View Dependent Claims (29)
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30. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;
wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture;
wherein the eight 32-bit general purpose registers include the EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI registers; and
wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture. - View Dependent Claims (31)
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32. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register, wherein the prefix portion comprises an extended register prefix byte, and wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register. - View Dependent Claims (33)
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34. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers;
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;
a control register for storing information indicating whether or not the extended register mode is globally enabled;
a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and
generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.
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35. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;
wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture. - View Dependent Claims (36)
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37. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;
wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register. - View Dependent Claims (38)
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39. A central processing unit (CPU) comprising:
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a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture;
an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;
a control register for storing information indicating whether or not the extended register mode is globally enabled;
a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and
generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.
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Specification