Central processing unit (CPU) accessing an extended register set in an extended register mode

• US 6,877,084 B1
• Filed: 04/02/2001
• Issued: 04/05/2005
• Est. Priority Date: 08/09/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Christie, David S.
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/824,863
• Time in Patent Office: 1,464 Days
• Field of Search: 712/43, 712/203, 712/210, 712/229, 712/213, 712/300, 711/125, 711/212, 711/173, 711/172
• US Class Current: 712/203
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag

Abstract

A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended register set. The standard register set includes multiple standard registers, and the extended register set include multiple extended registers. The execution core fetches and executes instructions, and receives a signal indicating an operating mode of the CPU. The execution core responds to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register. The standard registers may be general purpose registers of a CPU architecture associated with the instruction. The number of extended registers may be greater than the number of general purpose registers defined by the CPU architecture. In this case, the additional register identification information in the prefix portion is needed to identify a selected one of the extended registers. A width of the extended registers may also be greater than a width of the standard registers. In this case, the prefix portion may also include an indication that the entire contents of the least one extended register is to be accessed. In this way, instruction operand sizes may selectively be increased when the CPU is operating in the extended register mode. A computer system including the CPU is also described.

Claims

1. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;

wherein the number of standard registers is less than or equal to a number of general purpose registers defined by a CPU architecture, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture.

2. The CPU as recited in claim 1, wherein the instruction absent the prefix portion includes register identification information sufficient to identify a selected one of the standard registers, and wherein the prefix portion of the instruction includes additional register identification information needed to identify a selected one of the extended registers.

3. The CPU as recited in claim 1, wherein the encoding of the instruction, including the prefix portion, identifies the at least one extended register accessed by the execution core.

4. The CPU as recited in claim 1, wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture.

5. The CPU as recited in claim 4, wherein the eight 32-bit general purpose registers include the EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI registers.

6. The CPU as recited in claim 4, wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture.

7. The CPU as recited in claim 1, wherein the execution core is configured to fetch and execute variable-length x86 instructions.

8. The CPU as recited in claim 1, wherein the prefix portion comprises an extended register prefix byte, and wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register.

9. The CPU as recited in claim 8, wherein the extended register prefix byte includes the information needed to access the at least one extended register only when the extended register key field contains a predetermined extended register key value.

10. The CPU as recited in claim 1, further comprising:

a control register for storing information indicating whether or not the extended register mode is globally enabled;

a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and

generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.

11. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;

wherein the instruction absent the extended register prefix byte includes register identification information sufficient to identify a selected one of the standard registers, and wherein the extended register prefix byte includes additional register identification information needed to identify a selected one of the extended registers.

12. The CPU as recited in claim 11, wherein the encoding of the instruction, including the extended register prefix byte, identifies the at least one extended register accessed by the execution core.

13. The CPU as recited in claim 11, wherein the standard register set comprises the EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI registers defined by the x86 architecture.

14. The CPU as recited in claim 11, wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture.

15. The CPU as recited in claim 11, wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register.

16. The CPU as recited in claim 15, wherein the extended register prefix byte includes the information needed to access the at least one extended register only when the extended register key field contains a predetermined extended register key value.

17. The CPU as recited in claim 11, further comprising:

a control register for storing information indicating whether or not the extended register mode is globally enabled;

a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and

generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.

18. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of general purpose registers defined by a CPU architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the CPU architecture, and wherein a width of the extended registers is greater than a width of the general purpose registers defined by the CPU architecture; and

an execution core coupled to the register file and to receive the signal indicating the operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing the entire contents of at least one extended register if;

(i) the signal indicates the CPU is operating in an extended register mode, (ii) the instruction includes a prefix portion including information needed to access the at least one extended register, and (iii) the prefix portion includes an indication that the entire contents of the least one extended register is to be accessed.

19. The CPU as recited in claim 18, wherein the CPU architecture is the x86 architecture, and wherein the width of the general purpose registers is 32 bits, and wherein the width of the extended registers is 64 bits.

20. The CPU as recited in claim 19, wherein the standard register set includes the EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI registers defined by the x86 architecture.

21. The CPU as recited in claim 20, wherein the standard register set is a subset of the extended register set, and wherein the standard registers form lower ordered portions of extended registers.

22. The CPU as recited in claim 18, wherein the instruction absent the prefix portion includes register identification information sufficient to identify a selected one of the standard registers, and wherein the prefix portion of the instruction includes additional register identification information needed to identify a selected one of the extended registers.

23. The CPU as recited in claim 18, wherein the encoding of the instruction, including the prefix portion, identifies the at least one extended register accessed by the execution core.

24. The CPU as recited in claim 18, wherein the execution core is configured to fetch and execute variable-length x86 instructions.

25. The CPU as recited in claim 18, wherein the prefix portion comprises an extended register prefix byte, and wherein the extended register prefix byte comprises:

(i) an extended register key field, wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register, and (ii) an operand size override bit, wherein the value of the operand size override bit indicates whether or not the entire contents of the least one extended register is to be accessed.

26. The CPU as recited in claim 18, wherein the extended register prefix byte includes the information needed to access the at least one extended register and the indication that the entire contents of the least one extended register is to be accessed only when the extended register key field contains a predetermined extended register key value.

27. The CPU as recited in claim 18, further comprising:

a control register for storing information indicating whether or not the extended register mode is globally enabled;

a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and

generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.

28. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;

wherein the instruction absent the prefix portion includes register identification information sufficient to identify a selected one of the standard registers, and wherein the prefix portion of the instruction includes additional register identification information needed to identify a selected one of the extended registers.

29. The CPU as recited in claim 28, wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture.

30. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;

wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture;

wherein the eight 32-bit general purpose registers include the EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI registers; and

wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture.

31. The CPU as recited in claim 30, wherein the instruction absent the prefix portion includes register identification information sufficient to identify a selected one of the standard registers, and wherein the prefix portion of the instruction includes additional register identification information needed to identify a selected one of the extended registers.

32. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register,

wherein the prefix portion comprises an extended register prefix byte, and wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register.

33. The CPU as recited in claim 32, wherein the extended register prefix byte includes the information needed to access the at least one extended register only when the extended register key field contains a predetermined extended register key value.

34. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of standard registers, and wherein the extended register set comprises a plurality of extended registers;

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register;

a control register for storing information indicating whether or not the extended register mode is globally enabled;

a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and

generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.

35. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;

wherein the standard register set comprises eight 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set includes the eight 32-bit general purpose registers of the standard register set and eight additional 32-bit registers not defined by the x86 architecture.

36. The CPU as recited in claim 35, wherein the instruction absent the extended register prefix byte includes register identification information sufficient to identify a selected one of the standard registers, and wherein the extended register prefix byte includes additional register identification information needed to identify a selected one of the extended registers.

37. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture; and

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;

wherein the extended register prefix byte comprises an extended register key field, and wherein the contents of the extended register key field indicates whether or not the extended register prefix byte includes the information needed to access the at least one extended register.

38. The CPU as recited in claim 37, wherein the extended register prefix byte includes the information needed to access the at least one extended register only when the extended register key field contains a predetermined extended register key value.

39. A central processing unit (CPU) comprising:

a register file including a standard register set and an extended register set, wherein the standard register set comprises a plurality of 32-bit general purpose registers defined by the x86 architecture, and wherein the extended register set comprises a plurality of extended registers, and wherein the number of extended registers is greater than the number of general purpose registers defined by the x86 architecture;

an execution core coupled to the register file and to receive a signal indicating an operating mode of the CPU, wherein the execution core is configured to fetch and execute variable-length x86 instructions, and wherein the execution core is configured to respond to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes an extended register prefix byte including information needed to access the at least one extended register;

a control register for storing information indicating whether or not the extended register mode is globally enabled;

a flags register for storing information indicating whether or not the extended register mode is enabled by a current process; and

generating means for generating the signal indicating the operating mode of the CPU, wherein the signal indicates the CPU is operating in the extended register mode if the extended register mode is globally enabled and enabled by the current process.