Automated approach to constraint generation in IC design

• US 6,877,139 B2
• Filed: 03/14/2003
• Issued: 04/05/2005
• Est. Priority Date: 03/18/2002
• Status: Expired due to Fees

• Current Assignee: Fishtail Design Automation Inc.
• Original Assignee: Fishtail Design Automation Inc.
• Inventors: Daga, Ajay Janami
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US10/390,194
• Publication Number:
  US 20030177463A1
• Time in Patent Office: 753 Days
• Field of Search: 716/1, 716/6
• US Class Current: 716/108
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A software-based system for generating timing constraints for a proposed IC design has a first input as a synthesizable description of the proposed IC, a second input as a clock specification for the proposed IC, and a processing unit accepting the first and second inputs, and determining therefrom as an output, a set of timing constraints to guide implementation of the proposed IC design.

Claims

1. A software-based system for generating timing constraints for a proposed IC design, comprising:

a first input as a synthesizable description of the proposed IC design;

a second input as a clock specification for the proposed IC design; and

a processing unit accepting the first and second inputs, and determining therefrom as an output a set of timing constraints to guide implementation of the proposed IC design;

wherein the processing unit, in determining the timing constraints, determines exceptions to single-cycle clocking for the proposed IC design.

2. The system of claim 1 wherein the exceptions include false paths and multi-cycle paths.

3. The system of claim 1 wherein the output is provided in Synopsys Design Constraint (SDC) format useable by one or more of virtual prototyping, logic synthesis, place &

route, and static timing tools in design implementation.

4. The system of claim 1 wherein the proposed IC design is one of an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

5. The system of claim 1 wherein the first and second inputs and output timing constraints are for an individual functional block on an IC instead of for the entire IC.

6. The system of claim 1 wherein the first and second inputs and output timing constraints are for paths between functional blocks on an IC.

7. The system of claim 6 wherein results are used to partition overall IC timing requirements into block timing budgets.

8. The system of claim 1 wherein the synthesizable description is provided as one of Verilog or VHDL format.

9. The system of claim 1 wherein the first input is derived from a .lib model, and converted into one of Verilog or VHDL format.

10. The system of claim 9 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detail.

11. The system of claim 1 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the proposed IC design to which a clock is applied.

12. A method for guiding an implementation phase for a proposed IC design, comprising the steps of:

(a) providing to a processing unit as a first input a synthesizable description of the proposed IC design;

(b) providing as a second input to the processing unit clock specification for the proposed IC design; and

(c) using the first and the second inputs by the processing unit to determine therefrom, as an output, a set of timing constraints to guide implementation of the proposed IC design, wherein, the processing unit, in determining the timing constraints, determines exceptions to single-cycle clocking for the proposed IC design.

13. The method of claim 12 wherein the exceptions include false paths and multi-cycle paths.

14. The method of claim 12 wherein the output is provided in Synopsys Design Constraint (SDC) format useable by one or more of virtual prototyping, logic synthesis, place &

route, and static timing tools in design implementation.

15. The method of claim 12 wherein the proposed IC design is one of an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

16. The method of claim 12 wherein the first and second inputs and output timing constraints are for an individual functional block on an IC instead of for the entire IC.

17. The method of claim 12 wherein the first and second inputs and output timing constraints are for interaction paths between functional blocks on an IC.

18. The system of claim 17 wherein results are used to partition overall IC timing requirements into block timing budgets.

19. The method of claim 12 wherein the synthesizable description is provided as one of Verilog or VHDL format.

20. The method of claim 12 wherein the first input is derived from a .lib model, and converted into one of Verilog or VHDL format.

21. The method of claim 20 wherein a facility is provided for a user to manually refine an automatically-generated model by adding functional detail.

22. The method of claim 12 wherein, as part of the clock specification users define the clocks, their periods, their phase shifts relative to a reference clock, and the nets on the proposed IC design to which a clock is applied.