Technique to assess timing delay by use of layout quality analyzer comparison

• US 6,877,147 B2
• Filed: 07/22/2002
• Issued: 04/05/2005
• Est. Priority Date: 07/22/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Dias, Nathan D., Kidd, David A., Page, Matthew J.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/200,365
• Publication Number:
  US 20040015805A1
• Time in Patent Office: 988 Days
• Field of Search: 716/6, 716/11, 716/12, 716/13, 716/14, 716/2, 716/5, 716/7, 713/401, 703/15
• US Class Current: 716/113
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.

Claims

1. A method comprising:

computing a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm, but omitting from computing a route for a net if a computation time is to exceed a timeout value; and

comparing each of the first plurality of routes not omitted to a corresponding route of a second plurality of routes, each of the second plurality of routes corresponding to the respective net of the plurality of nets, but currently existing in the integrated circuit layout;

identifying one or more routes from the second plurality of routes having a predetermined measurable difference from a corresponding one or more routes from the theoretically optimal routes, the predetermined measurable difference to affect timing delay in the integrated circuit layout.

2. The method as recited in claim 1 wherein the predetermined measurable difference measures connection length.

3. The method as recited in claim 1 wherein the predetermined measurable difference measures capacitance.

4. The method as recited in claim 1 wherein the predetermined measurable difference measures resistance.

5. The method as recited in claim 1 further comprising also omitting from computing one or more nets having a positive timing margin.

6. A computer readable medium comprising:

first instructions which, when executed, compute a first plurality of routes, each route of the first plurality of routes corresponding to a respective net of a plurality of nets in an integrated circuit layout, and each route representing a theoretically optimal route of the respective net according to a graph theory based algorithm, but the first instructions include instructions to omit from computing a route for a net if a computation time is to exceed a timeout value; and

second instructions which, when executed, compare each of the first plurality of routes not omitted to a corresponding route of a second plurality of routes, each of the second plurality of routes corresponding to the respective net of the plurality of nets, but currently existing in the integrated circuit layout;

third instructions which, when executed, identify one or more routes from the second plurality of routes having a predetermined measurable difference from a corresponding one or more routes from the theoretically optimal routes, the predetermined measurable difference to affect timing delay in the integrated circuit layout.

7. The computer readable medium as recited in claim 6 wherein the first instructions also omit from computing one or more nets having a positive timing margin.