Process for manufacturing a DMOS transistor
First Claim
1. A process for manufacturing a DMOS transistor (100) with a semiconductor body (5), which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type, and a first well region (20) of a first conductivity type directly adjoining and enclosing the source region (10), wherein a gate region (35) is formed on the surface of the surface layer of the semiconductor body (5), which gate region extends from the source region across at least part of the well region (20),said method comprising:
- starting on the surface of the semiconductor body (5), forming a trench-shaped structure in the surface layer by carrying out a dry plasma etching process, such that the trench-shaped structure includes a floor region, a source-end side wall extending from the floor region to the surface on a first side of the trench-shaped structure proximate to the source region, and a drain-end side wall on a second side of the trench-shaped structure proximate to the drain region, wherein said drain-end side wall region, said floor region and said source-end side wall region are continuous with one another and together form a drift region of said DMOS transistor, and wherein at least one of the side walls slopes non-perpendicularly relative to the surface so that the trench-shaped structure has a tapering cross-section with a greater width at the surface than at the floor region, wherein said width at the surface is greater than a death of said trench-shaped structure, and wherein said trench-shaped structure is located within an active portion of said DMOS transistor between said source region and said drain region;
producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure;
producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure; and
producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure;
wherein at least one of said concentration values is different from the others of said concentration values.
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Abstract
In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.
51 Citations
51 Claims
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1. A process for manufacturing a DMOS transistor (100) with a semiconductor body (5), which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type, and a first well region (20) of a first conductivity type directly adjoining and enclosing the source region (10), wherein a gate region (35) is formed on the surface of the surface layer of the semiconductor body (5), which gate region extends from the source region across at least part of the well region (20),
said method comprising: -
starting on the surface of the semiconductor body (5), forming a trench-shaped structure in the surface layer by carrying out a dry plasma etching process, such that the trench-shaped structure includes a floor region, a source-end side wall extending from the floor region to the surface on a first side of the trench-shaped structure proximate to the source region, and a drain-end side wall on a second side of the trench-shaped structure proximate to the drain region, wherein said drain-end side wall region, said floor region and said source-end side wall region are continuous with one another and together form a drift region of said DMOS transistor, and wherein at least one of the side walls slopes non-perpendicularly relative to the surface so that the trench-shaped structure has a tapering cross-section with a greater width at the surface than at the floor region, wherein said width at the surface is greater than a death of said trench-shaped structure, and wherein said trench-shaped structure is located within an active portion of said DMOS transistor between said source region and said drain region;
producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure;
producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure; and
producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure;
wherein at least one of said concentration values is different from the others of said concentration values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A process of manufacturing a DMOS transistor, comprising the steps:
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a) providing a semiconductor body having a surface;
b) etching a trench into said semiconductor body from said surface by carrying out a dry plasma etching process, so that said trench is bounded by first and second sidewalls respectively at first and second locations and a floor at a third location, wherein said first and second side walls extend from said surface to said floor, wherein said first and second side walls are non-parallel relative to each other and said trench has a tapering cross-section with a greater width between said first and second side walls at said surface than at said floor, and wherein said width is greater than a depth of said trench;
c) before and/or after said step b), implanting a dopant into said semiconductor body to result in a first dopant concentration of said dopant in a first wall region of said semiconductor body along said first location, a second dopant concentration of said dopant in a second wall region of said semiconductor body along said second location, and a third dopant concentration of said dopant in a floor region of said semiconductor body along said third location, wherein said first wall region, said floor region and said second wall region are continuous with one another and together form a drift region of said DMOS transistor, and wherein at least one of said dopant concentrations is different from the others of said dopant concentrations;
d) forming in said semiconductor body a source region adjacent to said first location;
e) forming in said semiconductor body a drain region adjacent to said second location;
f) forming in said semiconductor body a well region at a location underlying at least said source region, such that said well region directly adjoins and encloses said source region; and
g) forming a gate structure on said surface of said semiconductor body and adjoining said source region. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A process of manufacturing a DMOS transistor, comprising the steps:
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a) providing a semiconductor body having a surface;
b) implanting a first dopant into said semiconductor body to form a first doped region that is doped with said first dopant;
c) after said step b), etching a trench from said surface into said first doped region in said semiconductor body by carrying out a dry plasma etching process, so that said trench is bounded by a floor, a first side wall extending from said surface to said floor, and a second side wall extending from said surface to said floor, whereby a first wall region extending along said first side wall within said first doped region has a first dopant concentration of said first dopant and a second wall region extending along said second side wall within said first doped region has a second dopant concentration of said first dopant, and wherein a width of said trench is greater than a depth of said trench;
d) after said step c), implanting a second dopant through said trench into a floor region extending along said floor in said semiconductor body, so as to produce a third dopant concentration of said second dopant in said floor region;
e) forming in said semiconductor body a source region adjacent to said first side wall;
f) forming in said semiconductor body a drain region adjacent to said second side wall;
g) forming in said semiconductor body a well region underlying at least said source region, such that said well region directly adjoins and encloses said source region; and
h) forming a gate structure on said surface of said semiconductor body and adjoining said source region;
wherein said first wall region, said floor region and said second wall region are continuous with one another and together form a drift region of said DMOS transistor, and wherein at least one of said dopant concentration is different from the others of said dopant concentrations. - View Dependent Claims (50, 51)
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Specification