MOSgated device with accumulated channel region and Schottky contact

• US 6,878,994 B2
• Filed: 08/22/2003
• Issued: 04/12/2005
• Est. Priority Date: 08/22/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Thapar, Naresh
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/646,667
• Publication Number:
  US 20040119103A1
• Time in Patent Office: 599 Days
• Field of Search: 257/330, 257/331, 257/341, 257/476, 257/485, 257/486
• US Class Current: 257/330
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical N⁻ channel region disposed between an N⁺ source region and an N⁻ drift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the N⁺ region and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.

Claims

1. A MOSgated accumulation channel field effect transistor comprising a highly conductive silicon substrate of one of the conductivity types;

a drift region of said one of the conductivity types disposed above said substrate;

a channel region of said one of the conductivity types disposed above said drift region and having an impurity concentration less than that of said substrate;

a plurality of trenches extending through said channel regions and into said drift region;

each of said trenches having respective gate oxide liners alone their vertical walls, and insulation liners at the bottoms of said trenches;

a gate of the other conductivity type filling the interior of each of said trenches;

an insulation cap over the tops of each of said gates in each of said trenches;

a highly conductive source region disposed at the tops of the mesas between each of said trenches and above said channel regions which are in the mesas between each of said trenches;

a Schottky barrier contact area formed in the top of each of said mesas; and

a top contact metal connected to both said source regions and to said Schottky barrier contact areas;

wherein a Schottky barrier contact layer is disposed on said Schottky barrier contact area and is contacted by said top contact metal.

2. The transistor of claim 1, wherein said Schottky barrier contact layer is aluminum.

3. The transistor of claim 1, wherein said one of the conductivity types is the N type.

4. The transistor of claim 2, wherein said one of the conductivity types is the N type.

5. The transistor of claim 1, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

6. The transistor of claim 2, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

7. The transistor of claim 3, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

8. The transistor of claim 4, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

11. The device of claim 4, wherein said gates are formed of P type polysilicon.

12. The transistor of claim 11, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

9. A MOSgated accumulation channel field effect transistor comprising a highly conductive silicon substrate of one of the conductivity types;

a drift region of said one of the conductivity types disposed above said substrate;

a channel region of said one of the conductivity types disposed above said drift region and having an impurity concentration less than that of said substrate;

a plurality of trenches extending through said channel regions and into said drift region;

each of said trenches having respective gate oxide liners along their vertical walls, and insulation liners at the bottoms of said trenches;

a gate of the other conductivity type filling the interior of each of said trenches;

an insulation cap over the tops of each of said gates in each of said trenches;

a highly conductive source region disposed at the tops of the mesas between each of said trenches and above said channel regions which are in the mesas between each of said trenches;

a Schottky barrier contact area formed in the top of each of said mesas;

a top contact metal connected to both said source regions and to said Schottky barrier contact areas; and

first and second gate contacts for said gates filling said trenches;

said first gate contact connected to a first set of said gates;

said second gate connected to a second set of said gates.

10. The transistor of claim 9, which includes a second plurality of trenches formed in at least selected ones of said mesas and spaced from the walls of said trenches forming said mesas;

said Schottky barrier contact areas being formed in respective ones of said second plurality of trenches.

13. In a MOSgated accumulation channel field effect transistor having a plurality of mesas separated by parallel gate-filled trenches;

the tops of said mesas having a central Schottky barrier-receiving trench of relatively high resistivity surface flanked by source regions of relatively low resistivity surface; and

a top contact connected to said source region surface with an ohmic contact and to said Schottky barrier receiving trench surface with a Schottky contact;

wherein the Schottky barrier receiving trench is lined with a Schottky barrier material.

14. The transistor of claim 13, wherein the Schottky barrier material is aluminum.