Multi-die semiconductor package
First Claim
1. A semiconductor package comprising:
- an electrical interconnect frame having a top electrical contact level and a bottom electrical contact level, the top electrical contact level substantially parallel to and offset from the bottom electrical contact level, each of the top and bottom electrical contact levels having both a top surface and a bottom surface, a first integrated circuit die attached to a top surface of the top electrical contact level;
a second integrated circuit die attached to a bottom surface of the top electrical contact level;
a conductor having a first end connected to a pad on the second integrated circuit die and having a second end connected to a bottom surface of a structure of the top electrical contact level; and
a first wire having a first end connected to a pad on the first integrated circuit die and having a second end connected to a top surface of a structure of the bottom electrical contact level.
22 Assignments
0 Petitions
Accused Products
Abstract
A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.
34 Citations
23 Claims
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1. A semiconductor package comprising:
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an electrical interconnect frame having a top electrical contact level and a bottom electrical contact level, the top electrical contact level substantially parallel to and offset from the bottom electrical contact level, each of the top and bottom electrical contact levels having both a top surface and a bottom surface, a first integrated circuit die attached to a top surface of the top electrical contact level;
a second integrated circuit die attached to a bottom surface of the top electrical contact level;
a conductor having a first end connected to a pad on the second integrated circuit die and having a second end connected to a bottom surface of a structure of the top electrical contact level; and
a first wire having a first end connected to a pad on the first integrated circuit die and having a second end connected to a top surface of a structure of the bottom electrical contact level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor package comprising:
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a metal electrical interconnect frame including a substantially planar top electrical contact level having a first plurality of pads and including a substantially planar bottom electrical contact level having a second plurality of pads, the top electrical contact level substantially parallel to and offset from the bottom electrical contact level, both of the top and bottom electrical contact levels having a top surface and a bottom surface;
a first integrated circuit die having a top surface and a bottom surface, the bottom surface of the first integrated circuit die attached to the top surface of the top electrical contact level, the top surface of the first integrated circuit die having a plurality of pads wire bonded to the second plurality of pads; and
a second integrated circuit die having a top surface and a bottom surface, the bottom surface of the second integrated circuit die attached to a bottom surface of the top electrical contact level, the top surface of the second integrated circuit die having a plurality of pads wire bonded to the first plurality of pads. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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Specification