Converting sensed signals

• US 6,879,056 B2
• Filed: 12/29/2000
• Issued: 04/12/2005
• Est. Priority Date: 12/29/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Menzel, Christoph P., Kemp, Christopher J.
• Primary Examiner(s): DeBeradinis, Robert L.
• Application Number:
  US09/751,993
• Publication Number:
  US 20020117895A1
• Time in Patent Office: 1,565 Days
• Field of Search: 307/10.1, 280/735, 181/282, 73/13.7, 324/679
• US Class Current: 307/10.1
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G01P 15/125 by capacitive pick-up

Abstract

A way of converting sensed signals to a desirable form of electrical signals is provided that includes providing an input signal to a common input terminal of a sensing block. The way comprises receiving a sensed signal from the sensing block in response to applying the input signal.

Claims

1. An apparatus comprising:

an input block to apply an input signal to a common input terminal of a sensing block, the input block coupled to apply a first signal to the common input terminal during a first clock phase of a first clock and a second signal during a second clock phase of a second clock; and

a converting block to receive a sensed signal from the sensing block in response to the input signal.

2. The apparatus of claim 1, wherein the converting block is coupled to provide an output signal based on the sensed signal.

3. The apparatus of claim 1, wherein the converting block comprises an integrator to integrate the sensed signal and provide a first output signal and a second output signal.

4. The apparatus of claim 3, wherein the converting block is further configured to compare the first output signal and the second output signal and provide an output signal.

5. The apparatus of claim 4, wherein the converting block is coupled to provide the output signal to the input block.

6. The apparatus of claim 1, wherein the input block comprises a first input capacitor and a second input capacitor, wherein the input block is coupled to provide a first input signal into the converting block through the first input capacitor and a second input signal into the converting block through the second input capacitor.

7. The apparatus of claim 1, further comprising a storage unit to store one or more voltage values to couple to a first input capacitor and a second input capacitor of the apparatus.

8. The apparatus of claim 7, wherein the voltage values comprise calibration voltages, the calibration voltages to couple to a first input capacitor and a second input capacitor.

9. The apparatus of claim 1, wherein the sensing block comprises a pair of output terminals to provide the sensed signal.

10. The apparatus of claim 1, wherein the first clock and the second clock are non-overlapping.

11. A method comprising:

providing a first signal to a common input terminal of a sensing block during a first clock phase of a first clock and a second signal to the common input terminal during a second clock phase of a second clock, wherein the first clock phase and the second clock phase have non-overlapping clock cycles;

receiving a sensed signal from the sensing block based on providing the first signal and the second signal; and

providing a signal based on the sensed signal.

12. The method of claim 11, comprising integrating the sensed signal and providing a first output signal and a second output signal.

13. The method of claim 12, comprising comparing the first output signal and the second output signal to provide an output signal.

14. The method of claim 13, comprising providing the first signal and second signal based at least in part on the output signal.

15. The method of claim 11, further comprising directly providing the first signal using a first reference voltage and the second signal using a second reference voltage.

16. The method of claim 11, further comprising calibrating the sensing block using a first input capacitor and a second input capacitor.

17. A restraint system, comprising:

a sensing circuit to;

apply an input signal to a common input terminal of a sensing block;

receive a sensed signal from the sensing block in response to applying the input signal; and

provide an output signal based at least in part on the sensed signal;

a deployment block to provide an activation signal based at least in part on the output signal from the sensing circuit; and

a control unit to provide a control signal to the deployment block.

18. The restraint system of claim 17, wherein the deployment block is coupled to provide the activation signal to activate an airbag.

19. The restraint system of claim 17, wherein the sensing circuit is coupled to be clocked via a plurality of non-overlapping clocks.

20. The restraint system of claim 17, wherein the sensing circuit is configured to provide a digital signal.

21. The restraint system of claim 17, wherein the sensing circuit is coupled to provide a signal having a fractional pulse density that is indicative of acceleration.

22. The restraint system of claim 17, further comprising a storage unit to store one or more voltage values to apply to the sensing circuit.

23. The restraint system of claim 17, wherein the sensing block comprises a pair of output terminals to provide the sensed signal.