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Word line arrangement having multi-layer word line segments for three-dimensional memory array

  • US 6,879,505 B2
  • Filed: 03/31/2003
  • Issued: 04/12/2005
  • Est. Priority Date: 03/31/2003
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

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