Word line arrangement having multi-layer word line segments for three-dimensional memory array

• US 6,879,505 B2
• Filed: 03/31/2003
• Issued: 04/12/2005
• Est. Priority Date: 03/31/2003
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/403,844
• Publication Number:
  US 20040190360A1
• Time in Patent Office: 743 Days
• Field of Search: 365/51, 365/63, 365/96, 365/105, 365/175, 365/230.06, 365/230.08, 257/390, 257/401
• US Class Current: 365/51
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Claims

1. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

2. The integrated circuit of claim 1 wherein each respective word line comprises at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

3. The integrated circuit of claim 1 comprising anti-fuse memory cells.

4. The integrated circuit of claim 1 comprising fuse memory cells.

5. The integrated circuit of claim 1 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

6. The integrated circuit of claim 5 wherein at most one memory cell of a simultaneously programmed group of memory cells is coupled to an individual word line segment.

7. The integrated circuit of claim 5 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

8. The integrated circuit of claim 1 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

9. The integrated circuit of claim 1 wherein the memory array comprises a plurality of array blocks and the word line segments in each array block are interleaved.

10. The integrated circuit of claim 9 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

11. The integrated circuit of claim 9 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

12. The integrated circuit of claim 11 including word lines respectively comprising at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

13. The integrated circuit of claim 12 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

14. The integrated circuit of claim 13 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

15. The integrated circuit of claim 1 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

16. The integrated circuit of claim 15 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

17. The integrated circuit of claim 1 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

18. The integrated circuit of claim 17 wherein:

each block includes a respective plurality of N selected bias lines; and

each select node of the multi-headed word line decoder circuit is coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

19. The integrated circuit of claim 18 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

20. The integrated circuit of claim 19 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

21. The integrated circuit of claim 18 wherein each memory block includes an unselected bias line shared by all word line driver circuits associated with the block.

22. The integrated circuit of claim 1 wherein each of said bit lines traverses across an array block.

23. The integrated circuit of claim 1 wherein each of said bit lines is segmented, being operably coupled to an associated global bit line disposed on another layer of the array.

24. An integrated circuit comprising a three-dimensional programmable memory array having at least two word line layers, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on every word line layer.

25. The integrated circuit of claim 24 wherein the memory array comprises a passive element memory cell array.

26. The integrated circuit of claim 25 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

27. The integrated circuit of claim 24 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

28. The integrated circuit of claim 24 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

29. The integrated circuit of claim 28 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

30. The integrated circuit of claim 28 wherein the word line segments in each array block are interleaved.

31. The integrated circuit of claim 30 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

32. The integrated circuit of claim 28 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

33. The integrated circuit of claim 32 wherein at most one memory cell of a simultaneously programmed group of memory cells is coupled to an individual word line segment.

34. The integrated circuit of claim 32 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

42. The integrated circuit of claim 25 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on at least one associated bit line layer.

44. The method of claim 34 wherein the memory cells compromise anti-fuse memory cells.

35. A method for programming a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer, said method comprising the steps of:

selecting a word line in the array;

selecting at least two bit lines associated with the selected word line;

coupling the selected word line to a source of a suitable programming bias level;

coupling each of the selected bit lines to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby simultaneously program multiple memory cells coupled to the selected word line.

36. The method of claim 35 wherein each simultaneously programmed memory cell is associated with a different word line segment of the selected word line.

43. The method of claim 35 wherein the simultaneously programmed memory cells include at least two associated with a single bit line layer.

45. The method of claim 35 wherein coupling the selected word line comprises driving the selected word line by an N-channel transistor to the source of the suitable programming bias level.

46. The method of claim 35 wherein coupling the selected word line comprises:

driving the selected word line to a selected bias line; and

driving the selected bias line to the source of the suitable programming bias level by a respective first circuit arranged to initially drive the selected bias line from an unselected bias level toward the suitable programming bias level, and by a second circuit for subsequently providing a lower impedance path to a suitable programming bias level.

47. The method of claim 46 wherein the second circuit comprises a plurality of spatially distributed circuits.

37. A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each segmented word line comprising at least one word line segment on each of at least two word line layers that are connected together, said memory array comprising memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of two associated bit line layers, each bit line layer being associated with at most one word line layer.

38. The computer readable medium of claim 37 wherein each respective word line comprises at least one word line segment on each word line layer connected together by way of a respective single vertical connection.

39. The computer readable medium of claim 37 wherein the encoded integrated circuit comprises anti-fuse memory cells.

40. The computer readable medium of claim 37 wherein the encoded integrated circuit comprises fuse memory cells.

41. The computer readable medium of claim 37 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.