Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation

• US 6,879,516 B2
• Filed: 02/24/2004
• Issued: 04/12/2005
• Est. Priority Date: 08/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nejad, Hasan, Seyyedy, Mirmajid
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/784,785
• Publication Number:
  US 20040165461A1
• Time in Patent Office: 413 Days
• Field of Search: 365/171, 365/158, 365/161, 365/63, 365/225.5, 365/232
• US Class Current: 365/171
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Claims

1. A method of reading a resistive memory device comprising a plurality of memory slices of resistive memory cells, each slice comprising an array of memory cells arranged in rows and columns and having an associated access transistor, said method comprising

decoding a selected memory cell address as a column select signal, a row select signal, and a layer select signal;

using said layer select signal to select one of said layers for a read operation;

using said row select signal to select a row of memory cells of said selected one layer; and

using said column select signal to select a same column of memory cells in each of said layers by turning on said access transistor coupled to said same columns column.

2. A method as in claim 1, wherein said resistive memory cells are MRAM memory cells.

3. A method as in claim 2 further comprising sensing a resistance value of a selected memory cell with a sense amplifier coupled to said access transistor.

4. A method of reading a resistive memory device comprising a plurality of memory slices of resistive memory cells, each memory slice comprising an array of memory cells arranged in rows and columns, said method comprising:

identifying a selected memory cell in said resistive memory device;

addressing said selected memory cell in said resistive memory device;

enabling an access gate corresponding to a memory slice including the selected memory cell;

coupling said memory cell to an input of a sense amplifier; and

coupling a reference line to a second input of said sense amplifier.

5. The method of said 4 wherein said access gate is a transistor.

6. The method of said 4, wherein said identifying comprises a determination of said memory slice containing the selected memory cell.

7. The method of said 4, wherein said identifying comprises a determination of a row, column and array layer of the selected memory cell.

8. The method of said 4, further comprising the step of determining the logic of said selected memory cell.

9. The method of said 8, wherein said determining the logic step comprises sensing a logic state of said selected memory cell.

10. The method of said 4, wherein said coupling said memory cell comprises:

coupling said selected memory cell to a sense line associated with said selected memory cell.

11. The method of said 10, wherein said coupling said memory cell further comprises:

coupling said sense line to an associated sense line interconnect.

12. The method of said 11, wherein said coupling said memory cell further comprises:

coupling said sense line interconnect to said access gate.

13. The method of said 12, wherein said coupling said memory cell further comprises:

coupling said access gate to an associated bit line.

14. The method of said 13, wherein said coupling said memory cell further comprises:

coupling said bit line to said input of said sense amplifier.

15. A method of reading a resistive memory device comprising a plurality of memory slices of MRAM memory cells, each memory slice comprising an array of memory cells arranged in rows and columns and having an associated access transistor, said method comprising:

decoding a selected memory cell address as a column select signal, a row select signal, and a layer select signal;

enabling a read/write row line associated with said selected memory cell in one of said plurality of memory slices;

coupling a sense line with said selected memory cell; and

determining a logic state of said selected memory cell.

16. The method of said 15, wherein said determining said logic state comprises sensing a resistance of said selected memory cell.

17. The method of said 15, said sensing said logic state comprises sensing magnetic moments of said selected memory cell.