Embedded memory with security row lock protection

• US 6,879,518 B1
• Filed: 11/21/2003
• Issued: 04/12/2005
• Est. Priority Date: 11/21/2003
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Curry, Duncan
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/718,748
• Time in Patent Office: 508 Days
• Field of Search: 365/185.04, 365/185.33, 365/195, 365/196, 711/152, 711/163
• US Class Current: 365/185.04
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A memory device having a memory array of nonvolatile memory elements also includes one or more security rows (or columns) of security bits that can be programmed to a locked status. External memory access requests are processed by first reading the corresponding security bit. If the requested row or column is locked, a default zero value is returned. Only external requests of unlocked locations, and all internal access requests, return the actual memory contents. Security bits can be erased (unlocked), but the secured contents of the locked row or column is also erased at the same time.

Claims

1. A semiconductor memory comprising:

an array of first memory elements including bit lines coupled with corresponding columns of elements in the array and word lines coupled with corresponding rows of elements in the array, each of the first memory elements holding data, said array further including a security row of second memory elements coupled to a corresponding security word line, each of the second memory elements being coupled to the bit lines of the array of first memory elements, said second memory elements being programmed in a first mode of operation to allow the data in the first memory elements to be read, said second memory elements being programmed in a second mode of operation to prevent the data in the first memory elements from being read; and

means for selecting the security row to operate in either the first mode of operation or the second mode of operation.

2. The semiconductor memory of claim 1 wherein the security row is selected for read when an external read command is requested and deselected when an internal read command is requested.

3. The method of claim 1 wherein the second mode of operation includes returning a default zero value in response to an external read request of said memory.

4. The semiconductor memory of claim 1 wherein the means for selecting includes a chip erase command to program the second memory elements to operate in the first mode of operation.

5. The semiconductor memory of claim 1 wherein the means for selecting includes a write lockbit command to program the second memory elements to operate in the second mode of operation.

6. The semiconductor memory of claim 1 further including a security row of third memory elements coupled to a corresponding security bit line, each of the third memory elements coupled to the word lines of the array of the second memory elements, said third memory elements being programmed in a first mode of operation to allow the data in the first memory elements to be read, said third memory elements being programmed in a second mode of operation to prevent the data in the first memory elements from being read.

7. The semiconductor memory of claim 6 further comprising means for erasing of the first memory elements followed the second and third memory elements such that the previous data contents are destroyed before the second and third memory elements operate in the first mode of operation.

8. The semiconductor memory of claim 6 wherein the security row of third memory elements is selected for reading at appropriate times so as to determine a mode of operation of the third memory elements.

9. The semiconductor memory of claim 1 further comprising a plurality of security rows distributed across the array.

10. A method of operating an embedded semiconductor memory comprising:

having security lock protection responsive to an external access request to said memory; and

disabling external access to a memory array row whenever a security bit in a security row indicates a locked status, and otherwise enabling access to the memory array.

11. The method of claim 10 wherein internal access is enabled regardless of locked/unlocked status.

12. The method of claim 10 further comprising erasing memory contents of said memory prior to resetting security row memory cell elements and lock bit cells to an unlocked status.

13. The method of claim 10 wherein a chip erase command erases and unlocks all security bits at the same rate and in the same manner as all elements in the memory array are erased.

14. The method of claim 10 wherein a lockbit sense amplifier is selected to detect and latch the locked or unlocked status of the lockbit cells.