Threshold voltage adjustment method of non-volatile semiconductor memory device and non-volatile semiconductor memory device
First Claim
1. A threshold voltage adjustment method of a non-volatile semiconductor memory device that has memory cells and conducts data erase of the memory cells by changing threshold voltage with electrical bias, the threshold voltage adjustment method adjusting the threshold voltage to the memory cells after the data erase and comprising steps of:
- drain voltage applying step for applying drain voltage to drain terminals of the memory cells;
comparing step for comparing the drain voltage to be applied to the drain terminals with predetermined drain voltage; and
gate voltage applying step for controlling the drain voltage applying step by applying variable gate voltage to gate terminals of the memory cells in accordance with a comparison result obtained in the comparing step.
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Accused Products
Abstract
It is intended to provide a nonvolatile semiconductor memory device which maintains the maximum number of over-erase memory cells which are conductive when adjusting the threshold voltage after data erase by controlling the gate voltage of a memory cell continuously in order to adjust the threshold voltage in a short time and a nonvolatile voltage adjustment method. There is formed a feedback loop for controlling the number of memory cells to be conductive in a memory cell group by controlling a gate voltage generating circuit through a differential amplifier from a drain terminal and the gate voltage generating circuit is controlled by the differential amplifier so as to maintain the drain voltage at a predetermined drain voltage VRF. A variable gate voltage can be controlled continuously by a feedback loop for controlling the variable gate voltage based on a difference voltage between the drain voltage and the predetermined drain voltage. Thus, effective threshold voltage adjustment operation is enabled corresponding to a current supply capacity regardless of the current supply capacity of the drain voltage generating circuit.
12 Citations
20 Claims
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1. A threshold voltage adjustment method of a non-volatile semiconductor memory device that has memory cells and conducts data erase of the memory cells by changing threshold voltage with electrical bias, the threshold voltage adjustment method adjusting the threshold voltage to the memory cells after the data erase and comprising steps of:
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drain voltage applying step for applying drain voltage to drain terminals of the memory cells;
comparing step for comparing the drain voltage to be applied to the drain terminals with predetermined drain voltage; and
gate voltage applying step for controlling the drain voltage applying step by applying variable gate voltage to gate terminals of the memory cells in accordance with a comparison result obtained in the comparing step. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A non-volatile semiconductor memory device conducting data erase of memory cells by changing threshold voltage with electrical bias, for adjusting the threshold voltage of the memory cells after the data erase, the non-volatile semiconductor memory device comprising:
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a drain voltage generating section for supplying drain voltage to drain terminals of the memory cells, the drain voltage generating section being activated based on a threshold voltage adjusting signal;
a drain voltage detecting section for detecting the drain voltage; and
a gate voltage generating section for controlling variable gate voltage to be applied to gate terminals of the memory cells based on a drain voltage detecting signal from the drain voltage detecting section, the gate voltage generating section being activated based on the threshold voltage detecting signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification