Methods and apparatus for improved memory access
DCFirst Claim
1. An apparatus, comprising:
- at least one memory device having one or more outputs;
at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein the shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the shift frequency; and
wherein data from one or more of the outputs of the memory device is loaded into a corresponding shift register in one of the sets of shift registers and the loaded data is shifted from the shift register to a next one of the shift registers in the set according to the clock signal, such that the shift register maintains its shift frequency during any loading of the data.
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Abstract
A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.
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Citations
60 Claims
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1. An apparatus, comprising:
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at least one memory device having one or more outputs;
at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein the shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the shift frequency; and
wherein data from one or more of the outputs of the memory device is loaded into a corresponding shift register in one of the sets of shift registers and the loaded data is shifted from the shift register to a next one of the shift registers in the set according to the clock signal, such that the shift register maintains its shift frequency during any loading of the data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. An apparatus, comprising:
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at least one memory device having outputs;
at least a first set of shift registers interconnected in series and a second set of shift registers interconnected in series;
a plurality of connectors connecting one of the outputs of at least one of the memory devices to a corresponding shift register in the first or second set of shift registers; and
wherein data from at least one of the outputs of the memory devices are loaded into the corresponding shift register in the first or second sets of shift registers via the plurality of connectors;
wherein the data loaded into the first set of shift registers is shifted from one of the shift registers in the first set of shift registers to a next one of the shift registers in the first set of shift registers according to a clock signal; and
wherein the data loaded into the second set of shift registers is shifted from one of the shift registers in the second set of shift registers to a next one of the shift registers in the second set of shift registers according to the clock signal.
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38. A method, comprising:
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shifting data in one or more shift registers in a set of shift registers interconnected in series from the shift register to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency;
loading data from at least one memory device into a corresponding shift register in the set; and
shifting the data loaded into one or more of the shift registers to a next one of the shift registers in the set according to the clock signal, wherein the shift registers maintain their shift frequency during the loading of the data from the memory devices into the shift registers. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A method, comprising:
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shifting data in a first set of shift registers interconnected in series from the shift register to a next one of the shift registers in the first set on the basis of a clock signal having a shift frequency;
shifting data in a second set of shift registers interconnected in series from the shift register to a next one of the shift registers in the second set at the shift frequency;
loading data from at least one output of a memory device into a corresponding shift register in the first set;
loading data from at least one output of the memory device into a corresponding shift register in the second set;
shifting the data loaded into the shift register in the first set from the shift register to a next one of the shift registers in the first set according to the shift frequency; and
shifting the data loaded into the shift register in the second set from the shift register to a next one of the shift registers in the second set according to the shift frequency.
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52. An apparatus, comprising:
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at least one means for storing data including at least one means for transferring the data;
at least one set of a plurality of means for shifting data, wherein the means for shifting data receive a clock signal having a shift frequency and wherein the means for shifting in each are interconnected in series such that data from at least one of the means for shifting may be shifted to a next one of the means for shifting according to the shift frequency; and
means for loading the data from the means for storing into a corresponding means for shifting, such that the means for shifting maintain their frequency during the loading of data. - View Dependent Claims (53)
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54. A method, comprising:
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shifting data in one or more shift registers in a set of shift registers interconnected in series from the shift registers to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency;
loading data from one or more of the shift registers to a memory device; and
shifting the data loaded from the one or more shift registers to a next one of the shift registers in the set according to the shift frequency after the data is loaded into the memory device, wherein the shift registers maintains their shift frequency during the loading of the data.
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55. An apparatus, comprising:
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at least one memory device having one or more outputs;
at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein a shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the shift frequency; and
wherein data from one or more of the outputs of the memory device is loaded into a corresponding shift register in one of the sets of shift registers and the loaded data is shifted from the corresponding shift register to a next one of the shift registers in the set according to the clock signal, such that loading data into the shift registers occurs without disruption of the shift frequency of the shift registers.
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56. An apparatus, comprising:
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at least one memory device having outputs;
at least a first set of shift registers interconnected in series and a second set of shift registers interconnected in series;
a plurality of connectors connecting one of the outputs of at least one of the memory devices to a corresponding shift register in the first or second set of shift registers; and
wherein data from at least one of the outputs of the memory devices are loaded into a corresponding shift register in the first or second sets of shift registers via the plurality of connectors;
wherein the data loaded into the first set of shift registers is shifted from one of the shift registers in the first set of shift registers to a next one of the shift registers in the first set of shift registers according to a clock signal;
wherein the data loaded into the second set of shift registers is shifted from one of the shift registers in the second set of shift registers to a next one of the shift registers in the second set of shift registers according to the clock signal, and wherein loading data into the first set of shift registers and the second set of shift registers occurs without disruption of shifting according to the clock signal for the first set of shift registers and the second set of shift registers.
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57. A method, comprising:
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shifting data in one or more shift registers in a set of shift registers interconnected in series from a shift register to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency;
loading data from at least one memory device into a corresponding shift register in the set; and
shifting the data loaded into one or more of the shift registers to a next one of the shift registers in the set according to the clock signal, loading data into the shift registers occurs without disruption of the shift frequency of the shift registers.
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58. A method, comprising:
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shifting data in a first set of shift registers interconnected in series from a shift register in the first set to a next one of the shift registers in the first set on the basis of a clock signal having a shift frequency;
shifting data in a second set of shift registers interconnected in series from a shift register in the second set to a next one of the shift registers in the second set at the shift frequency;
loading data from at least one output of a memory device into a corresponding shift register in the first set;
loading data from at least one output of the memory device into a corresponding shift register in the second set;
shifting the data loaded into the corresponding shift register in the first set from the corresponding shift register in the first set to a next one of the shift registers in the first set according to the shift frequency; and
shifting the data loaded into the corresponding shift register in the second set from the corresponding shift register in the second set to a next one of the shift registers in the second set according to the shift frequency, wherein loading data into the corresponding shift register in the first set and the corresponding shift register in the second set occurs without disruption of the shift frequency for the first set of shift registers and the second set of shift registers.
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59. An apparatus, comprising:
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at least one means for storing data including at least one means for transferring the data;
at least one set of a plurality of means for shifting data, wherein each means for shifting data receives a clock signal having a shift frequency and wherein the means for shifting are interconnected in series such that data from at least one of the means for shifting may be shifted to a next one of the means for shifting according to the shift frequency; and
means for loading the data from the means for storing into a corresponding means for shifting, such that loading data into the corresponding means for shifting data occurs without disruption of the shift frequency of the at least one set of a plurality of means for shifting data.
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60. A method, comprising:
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shifting data in one or more shift registers in a set of shift registers interconnected in series from a shift register to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency;
loading data from one or more of the shift registers to a memory device; and
shifting the data loaded from the one or more shift registers to a next one of the shift registers in the set according to the shift frequency as the data is loaded into the memory device, wherein loading data from the shift registers occurs without disruption of the shift frequency of the shift registers.
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Specification