Variable rate continuous mode satellite modem

• US 6,879,627 B1
• Filed: 06/01/2000
• Issued: 04/12/2005
• Est. Priority Date: 06/01/2000
• Status: Active Grant

• Current Assignee: Advantech Wireless Ltd.
• Original Assignee: Shiron Satellite Communications Limited
• Inventors: Davidson, Jeffrey, Pokrass, Alexander, Goldenberg, Sorin, Wayer, Israel Shahaf
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Vartanian, Harry
• Application Number:
  US09/584,746
• Time in Patent Office: 1,776 Days
• Field of Search: 375/222, 375/295, 375/219, 375/344, 375/152, 375/142, 342/357.09, 370/337
• US Class Current: 375/222
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 27/2272 using phase locked loops H04L27/2273 takes precedence

Abstract

A satellite modem whose baseband modules can be implemented mostly in software running on a suitable processor such as a high speed digital signal processor (DSP). The modem includes a RF portion and a baseband portion. The digitized output of a matched filter is input to the baseband processing portion that consists of software executing on a DSP. The modem comprises an antenna coupled to an upconverter/downconverter. The upconverter/downconverter is coupled to a RF transceiver which functions to receive a transmit signal from a baseband transmitter module and generate a signal for input to the upconverter/downconverter. The RF transceiver also functions to receive a downconverted signal and output an IF signal for input to an IF module. The IF functions to generate I and Q outputs that are input to a digital baseband module. The baseband module can be implemented as software executing on a DSP. Also included in a technique of modulation wipe off wherein the effects of modulation are removed. A signal detection technique performs signal detection and frequency acquisition in the presence of multiple signals in accordance with a method described hereinbelow. A timing acquisition technique includes an unwrapping technique that functions to correct timing errors before averaging is performed. Linear changes to the time estimates are performed using LSR techniques.

Claims

1. A receiver baseband apparatus, comprising:

an input unit adapted to receive an I and Q signal;

a first matched filter adapted to receive said I signal and generate an I filtered output therefrom;

a second matched filter adapted to receive said Q signal and generate a Q filtered output therefrom;

a processor programmed to perform the steps of;

detecting the presence of signal activity as input to said receiver baseband apparatus;

acquiring said signal activity by performing coarse phase acquisition on said signal activity once it is detected, wherein said performing coarse phase acquisition comprises;

rotating vectors z_n representing said signal activity into a single

quadrant by an angle Θ

k;

wiping off said z_n(Θ

k) modulation;

summing the wiped off vectors z_n(Θ

k);

determining the energy contained within a plurality of hypotheses; and

selecting a single hypothesis from said plurality of hypotheses having the maximum energy;

pre-tracking said signal activity once it is detected; and

tracking said signal activity once it is detected;

a decoder adapted to receive said I filtered output signal and said Q filtered output signal from said processor and to generate a decoded output therefrom;

a deinterleaver adapted to generate a deinterleaved output in accordance with said decoded output signal input thereto;

a forward error correction decoder adapted to generate output receive data in accordance with said deinterleaved output signal input thereto; and

a controller adapted to manage and control said input unit, first matched filter, second matched filter, said processor, said decoder, said deinterleaver and said forward error correction decoder.

2. A receiver baseband apparatus, comprising:

an input unit adapted to receive an I and Q signal;

an I matched filter adapted to receive said I signal and generate an I filtered output therefrom;

a Q matched filter adapted to receive said Q signal and generate a Q filtered output therefrom;

a processor programmed to;

perform automatic gain control (AGC) and generate an AG control signal therefrom;

perform timing detection and generate an analog to digital (A/D) clock control signal therefrom;

perform phase detection and generate a voltage controlled oscillator (VCO) control signal therefrom;

a decoder adapted to receive said I filtered output signal and said Q filtered output signal from said processor and to generate a decoded output therefrom;

a deinterleaver adapted to generate a deinterleaved output in accordance with said decoded output signal input thereto;

a forward error correction decoder adapted to generate output receive data in accordance with said deinterleaved output signal input thereto; and

a controller adapted to manage and control said input unit, I matched filter, Q matched filter, said processor, said decoder, said deinterleaver and said forward error correction decoder;

wherein said processor is further operable to acquire signal activity by performing coarse phase acquisition on said signal activity, wherein said performing coarse phase acquisition comprises;

rotating vectors z_n representing said signal activity into a single quadrant by an angle Θ

k;

wiping off said z_n(Θ

k) modulation;

summing the wiped off vectors z_n(Θ

k);

determining the energy contained within a plurality of hypotheses; and

selecting a single hypothesis from said plurality of hypotheses having the maximum energy.

3. The apparatus according to claim 2, wherein said processor is further operable to pre-track said signal activity by performing timing acquisition on K groups, each made up of N DFT estimates, each estimate calculated from blocks of 16 symbols, said performing timing acquisition comprising:

calculating estimate t_i based on a DFT for 16 contiguous symbols, i=1 . . . N,

thereby obtaining N DFT estimates each based on a block of symbols;

generating a histogram of said N DFT estimates t_i;

classifying range said group the N estimates are in based on said histogram;

unwrapping said N DFT estimates and calculating their average T_i; and

unwrapping K average estimates T_i and performing a least square fit of said K averages to generate a final estimate.