Synchronous network traffic processor
First Claim
Patent Images
1. A processor synchronous with an instruction clock signal, comprising:
- an execution control unit synchronous with the instruction clock signal and operable to execute an instruction per clock cycle of the instruction clock signal;
an input pipeline unit synchronous with the instruction clock signal and operable to receive a stream of input data words one data word per clock cycle of the instruction clock signal, the input pipeline unit further operable to selectively output one input data word per clock cycle of the instruction clock signal;
a data modify unit coupled to the input pipeline unit, the data modify unit operable to selectively modify input data words received from the input pipeline unit according to instruction-specified operators to generate modified data words one modified data word per clock cycle of the instruction clock signal;
a processor output selector operable to selectively output, at each clock cycle of the instruction clock signal, an instruction-specified one of the input data words and the modified data words; and
wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal.
16 Assignments
0 Petitions
Accused Products
Abstract
A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.
66 Citations
36 Claims
-
1. A processor synchronous with an instruction clock signal, comprising:
-
an execution control unit synchronous with the instruction clock signal and operable to execute an instruction per clock cycle of the instruction clock signal;
an input pipeline unit synchronous with the instruction clock signal and operable to receive a stream of input data words one data word per clock cycle of the instruction clock signal, the input pipeline unit further operable to selectively output one input data word per clock cycle of the instruction clock signal;
a data modify unit coupled to the input pipeline unit, the data modify unit operable to selectively modify input data words received from the input pipeline unit according to instruction-specified operators to generate modified data words one modified data word per clock cycle of the instruction clock signal;
a processor output selector operable to selectively output, at each clock cycle of the instruction clock signal, an instruction-specified one of the input data words and the modified data words; and
wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A processor synchronous with an instruction clock signal, the processor comprising:
-
an input pipeline unit operable to receive a plurality of input data words at a rate of one input data word per clock cycle of the instruction clock signal;
an execution control unit;
an instruction memory storing instructions for execution by the execution control unit, wherein the execution control unit is operable to execute, during each clock cycle of the instruction clock signal, one of the instructions so as to control an instruction-specified operation on an instruction-specified one of the input data words in the input pipeline unit, and wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during next clock cycle of the instruction clock signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A processor synchronous with an instruction clock signal, comprising:
-
an input pipeline unit operable to continuously receive a stream of input data words including one data word during each clock cycle of the instruction clock signal, the input pipeline unit further operable to output successive ones of the data words during successive clock cycles of the instruction clock signal;
a data modify unit coupled to the input pipeline unit, said data modify unit operable to selectively modify during each clock cycle of the instruction clock signal an input data word received from the input pipeline unit in accordance with an instruction specified operator and generating a resultant output data word;
a data compare unit coupled to the input pipeline unit, said data compare unit operable to selectively compare during each clock cycle of the instruction clock signal an input data word received from the input pipeline unit with an instruction specified operand and generating a resultant set of compare flags; and
an execution control unit, coupled to the data modify unit and data compare unit, the execution control unit operable to configure during each clock cycle of the instruction clock signal at least one of the data modify unit and the data compare unit in accordance with a current instruction, wherein the execution control unit is operable to repeating execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
-
Specification