Switching power planes of external device interfaces in a computing system in response to connection status
First Claim
1. A motherboard in a computing system, wherein said motherboard comprises:
- a circuit board including a main voltage plane segment and a separate voltage plane segment;
a microprocessor;
a port connector including a connection-sensing terminal;
switching means for selectively connecting said main voltage plane segment to said separate voltage plane segment, wherein said switching means connects said main voltage plane segment to said separate voltage plane segment in response to a determination that said connection-sensing terminal is externally grounded, and wherein switching means disconnects said main voltage plane segment from said separate voltage plane segment in response to a determination that said connection-sensing terminal is electrically floating; and
a device interface circuit conditioning signals transmitted between said microprocessor and said port connector, wherein said device interface circuit draws electrical power from said separate voltage plane segment.
2 Assignments
0 Petitions
Accused Products
Abstract
A computing system includes a motherboard including one or more connection subsystems, each of which includes a port connector and a device interface circuit conditioning signals transmitted or received through the port connector. The port connector includes a connection-sensing terminal, which is connected to ground through a cable, and which is allowed to float to a voltage supplied through a pull-up resistor when the cable is disconnected. The motherboard also includes a main voltage plane supplying electrical power to a separate voltage plane for each device interface circuit only when a cable is connected to the port connector which is also connected to the device interface circuit.
25 Citations
20 Claims
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1. A motherboard in a computing system, wherein said motherboard comprises:
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a circuit board including a main voltage plane segment and a separate voltage plane segment;
a microprocessor;
a port connector including a connection-sensing terminal;
switching means for selectively connecting said main voltage plane segment to said separate voltage plane segment, wherein said switching means connects said main voltage plane segment to said separate voltage plane segment in response to a determination that said connection-sensing terminal is externally grounded, and wherein switching means disconnects said main voltage plane segment from said separate voltage plane segment in response to a determination that said connection-sensing terminal is electrically floating; and
a device interface circuit conditioning signals transmitted between said microprocessor and said port connector, wherein said device interface circuit draws electrical power from said separate voltage plane segment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A motherboard in a computing system, wherein said motherboard comprises:
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a circuit board including a main voltage plane segment;
a microprocessor; and
a plurality of connection subsystems, wherein each connection system within said plurality of connection subsystems includes;
a separate voltage plane segment within said circuit board;
a port connector including a connection-sensing terminal;
switching means for selectively connecting said main voltage plane segment to said separate voltage plane segment, wherein said switching means connects said main voltage plane segment to said separate voltage plane segment in response to a determination that said connection-sensing terminal is externally grounded, and wherein switching means disconnects said main voltage plane segment from said separate voltage plane segment in response to a determination that said connection-sensing terminal is electrically floating; and
a device interface circuit conditioning signals transmitted between said microprocessor and said port connector, wherein said device interface circuit draws electrical power from said separate voltage plane segment. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A system configuration method for switching electrical power to each device interface circuit within a plurality of device interface circuits, wherein each said device interface circuit conditions signals transmitted between a microprocessor and a port connector electrically connected to said device interface circuit, and wherein said system configuration method comprises:
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for each said device interface circuit, setting a bit position associated with said device interface circuit in a first register to a first state in response to electrically grounding a connection-sensing terminal within said port connector connected to said device interface circuit and to a second state in response to electrically floating said connection-sensing terminal; and
for each device interface circuit within said plurality of device interface circuits, performing a port configuration method including;
reading said bit position associated with said device interface circuit within said first register;
reading a bit position associated with said device interface circuit within a second register;
setting a bit position associated with said device interface circuit in said second register to a third state in response to determining that said bit position associated with said device interface circuit in said first register is in said first state and that said bit position associated with said device interface circuit in said second register is in a fourth state;
setting said bit position associated with said device interface circuit in said second register to said fourth state in response to determining that said bit position associated with said device interface circuit in said first register is in said second state and that said bit position associated with said device circuit in said second register is in said third state;
turning a switching device on to conduct electrical power to said device interface circuit in response to setting said bit position associated with said device interface circuit in said second register to said third state; and
turning said switching device off in response to setting said bit p position associated with said device interface circuit in said second register to said fourth state. - View Dependent Claims (19, 20)
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Specification