Memory device test system and method
First Claim
1. A testing system comprising:
- a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test;
a pattern generator configured to produce an address signal; and
a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1;
wherein during a data read and compare generator, the pattern generator and the waveform shaping circuit are configured to;
(i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal;
wherein the wave form shaping circuit provides the address signal to the memory device for x cycles of the clock signal;
wherein the testing system produces the strobe signal during only one cycle of the x cycles of the clock signal;
wherein x is an integer; and
wherein the testing system is configured to first perform the read and compare operation for even addresses in an address space of the memory device, and to then perform the read and compare operation for odd addresses in the address space of the memory device.
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Abstract
A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device. In another embodiment, the first clock signal is not used and the address signals are synchronized to every two cycles of the second clock signal. A method for testing a memory device, which may be embodied in the testing system, is also described.
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Citations
29 Claims
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1. A testing system comprising:
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a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test;
a pattern generator configured to produce an address signal; and
a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1;
wherein during a data read and compare generator, the pattern generator and the waveform shaping circuit are configured to;
(i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal;
wherein the wave form shaping circuit provides the address signal to the memory device for x cycles of the clock signal;
wherein the testing system produces the strobe signal during only one cycle of the x cycles of the clock signal;
wherein x is an integer; and
wherein the testing system is configured to first perform the read and compare operation for even addresses in an address space of the memory device, and to then perform the read and compare operation for odd addresses in the address space of the memory device.
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2. A testing system comprising:
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a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test;
a pattern generator configured to produce an address signal; and
a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1;
wherein x is equal to 2;
wherein the clock signal comprises rising edge transition or a falling transition;
wherein the clock signal is asserted or either a rising edge transition or a falling edge transition of the clock signal; and
wherein the address signal remains asserted for two cycles of the clock signal after being asserted. - View Dependent Claims (3, 4, 5)
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6. A testing system, comprising:
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a timing generator constructed to generate a first clock signal;
a frequency multiplier circuit coupled to receive the first clock signal and configured to produce a second clock signal having a frequency greater than a frequency of the first clock signal, and to provide the second clock signal to a memory device;
a pattern generator coupled to receive the first clock signal and to produce an address signal; and
a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to the first clock signal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for testing a memory device, comprising:
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providing a clock signal to a memory device such that operation within the memory device are synchronized to the clock signal;
reading the data from the memory device using an address signal synchronized to every x cycles of the clock signal wherein x is greater than 1; and
comparing the data read from the memory device to test data;
wherein the providing comprises generating a clock signal having rising edge transitions and falling edge transitions; and
wherein the reading is preceded with writing test data to the memory device using the address signal, the address signal being asserted on either a rising edge transition or a falling edge transition of the first clock signal, and remaining asserted for at least one x cycles of the first clock signal alter being asserted. - View Dependent Claims (17)
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18. A method for testing a memory device comprising:
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providing a clock signal to a memory device such that operation within the memory device are synchronized to the clock signal;
reading the data from the memory device using an address signal synchronized to every x cycles of the clock signal wherein x is greater than 1; and
comparing the data read from the memory device to test data;
wherein the reading comprises providing the address signal to the memory device during the operation to retrieve data stored within the memory device at an address corresponding to the address signal, the address signal being provided to the memory device for x cycles of the clock signal; and
wherein the comparing comprises producing a strobe signal during only one cycle of the x cycles of the clock signal, to thereby acquire data from the memory device. - View Dependent Claims (19)
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20. A method for testing a memory device, comprising:
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using a first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;
providing the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal;
reading data from the memory device using an address signal synchronized to the first clock signal; and
comparing the data retrieved from the memory device during the reading to the test data. - View Dependent Claims (21, 22, 23, 24)
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25. A method for testing a memory device, comprising:
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providing a clock into the memory device;
inputting an address into the memory device, each address being synchronized with every two cycles of the clock;
outputting an output data from the memory device according to the address, the output data being synchronized with every cycle of the clock;
retrieving odd or even, but not both, of the output data; and
comparing the retrieved output data with corresponding even of a standard data. - View Dependent Claims (26, 27)
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28. A method for testing a memory device, comprising:
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generating a first clock signal;
using the first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;
providing the second clock signal to a memory device such that operations within the memory device are synchronized to the second clock signal;
performing a read and compare operation for each of the even addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data;
performing a read and compare operation for each of the odd addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address, wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data. - View Dependent Claims (29)
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Specification