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Method to detect systematic defects in VLSI manufacturing

  • US 6,880,136 B2
  • Filed: 07/09/2002
  • Issued: 04/12/2005
  • Est. Priority Date: 07/09/2002
  • Status: Expired due to Fees
First Claim
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1. A method for detecting systematic defects occurring on wafers having several chips which have a plurality of devices with scannable latches for logic testing comprising:

  • testing the logic for each device, and storing the latches that contained an incorrect logic value after completion of any test, as well as the identification of the associated failing tests;

    backtracing through a cone of logic from the latches having incorrect values;

    assigning a weighting value for objects encountered during backtracing to produce a vector of weights for each failing device;

    determining a fail signature based on the vector; and

    comparing fail signatures of any two failing devices to determine similarity of the failure.

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