Wire delay distributed model

• US 6,880,141 B1
• Filed: 04/06/2001
• Issued: 04/12/2005
• Est. Priority Date: 09/28/2000
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Tetelbaum, Alexander
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US09/827,434
• Time in Patent Office: 1,467 Days
• Field of Search: 716/6, 716/4, 716/1
• US Class Current: 716/113
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

An improved method of using the Elmore Model to estimate the delay which is associated with the a clock buffer output. The improved method provides that the clock buffer output resistor is taken into account when the Elmore Model is used to calculate the delay. Also provided is a method of using the Elmore Model to estimate wire delay, where the method includes steps of calculating an approximate delay based on a distributed RC model, and using a capacitance value corresponding to the approximate delay in the Elmore Model to estimate the wire delay.

Claims

1. A method for estimating wire delay, said method comprising:

formulating a distributed RC model;

calculating an approximate delay based on the distributed RC model;

calculating a capacitance value based on the approximate delay which has been calculated;

using the capacitance value in the Elmore Model to estimate the wire delay, calculating a wire delay using the Elmore Model without using a distributed RC model, and calculating clock skew error using the distributed delay which has been calculated and the wire delay which has been calculated using the Elmore Model without using a distributed RC model.

2. A method as recited in claim 1, further comprising calculating a time domain response relating to the wire.

3. A method as recited in claim 2, using the time domain response which has been calculated to calculate the approximate delay based on the distributed RC model.

4. A method a recited in claim 1, wherein the capacitance value which is calculated is a fraction of a total wire capacitance.

5. A method for calculating clock skew error comprising:

formulating a distributing RC model;

calculating an approximate delay based on the distributed RC model;

calculating a capacitance value based on the approximate delay which has been calculated;

using the capacitance value in the Elmore Model to estimate the wire delay; and

subtracting the wire delay which has been calculated using the Elmore Model without using a distributed RC model from the distributed delay which has been calculated in order to calculate clock skew error.

6. A method as recited in claim 5, further comprising calculating a time domain response relating to the wire.

7. A method as recited in claim 6, using the time domain response which has been calculated to calculate the approximate delay based on the distributed RC model.

8. A method as recited in claim 6, wherein the capacitance value which is calculated is a fraction of a total wire capacitance.

9. A method as recited in claim 6, further comprising calculating a wire delay using the Elmore Model without using a distributed RC model.

10. A method as recited in claim 9, further comprising calculating clock skew error using the distributed delay which has been calculated and the wire delay which has been calculated using the Elmore Model without using a distributed RC model.

11. A method for estimating wire delay, said method comprising:

formulating a distributed RC model;

calculating an approximate delay based on the distributed RC model;

calculating a capacitance value based on the approximate delay which has been calculated;

using the capacitance value in the Elmore Model to estimate the wire delay, calculating a Wire delay without using a distributed RC model;

ad calculating clock skew err using the distributed delay and wire delay which have been calculated.

12. A method as recited in claim 11, further comprising calculating a time domain response relating to the wire.

13. A method as recited in claim 12, using the time domain response which has been calculated to calculate the approximate delay based on the distributed RC model.

14. A method as recited in claim 11, wherein the capacitance value which is calculated is a fraction of a total wire capacitance.