Method of manufacturing a semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film

• US 6,881,633 B2
• Filed: 06/25/2004
• Issued: 04/19/2005
• Est. Priority Date: 12/27/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hokazono, Akira
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/875,310
• Publication Number:
  US 20040235229A1
• Time in Patent Office: 298 Days
• Field of Search: 438/303, 438/305, 438/595, 257/E21.435, 257/E21.346
• US Class Current: 438/285
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween;

forming shallow source/drain diffusion layer in those regions of said semiconductor substrate which are positioned on both sides of said gate electrode by means of ion implantation performed with said gate electrode used as a mask;

forming a first side-wall insulating film on said semiconductor substrate after formation of said shallow source/drain diffusion layers;

forming a second side-wall insulating film on said first side-wall insulating film;

etching back a laminate structure including said first side-wall insulating film and said second side-wall insulating film;

removing said second side-wall insulating film remaining on the side-wall portion of said gate electrode so as to form an L-shaped/reversed L-shaped side-wall structure consisting of said first side-wall insulating film covering said gate electrode side-wall portion and a part of the upper surface of said semiconductor substrate in the vicinity of said gate electrode;

forming a semiconductor layer thicker than said first side-wall insulating film on said semiconductor substrate by means of a selective epitaxial growth method so as to form an extending portion of said semiconductor layer on said first side-wall insulating film covering a part of the upper surface of said semiconductor substrate; and

forming deep source/drain diffusion layers in those portions of said semiconductor substrate which are positioned on both sides of said gate electrode by means of ion implantation performed with said gate electrode equipped with the side-wall structure used as a mask.

2. A method of manufacturing a semiconductor device according to claim 1, further comprising forming a buried device isolation region consisting of a trench having an insulating film buried therein and positioned contiguous to the outer peripheral portion of said deep source/drain diffusion layers, wherein the process of forming said buried device isolation region comprises:

forming a trench in a semiconductor substrate;

burying a first insulating film having a seam in a central portion of said trench width along the inner wall of said trench;

removing said first insulating film deposited outside said trench so as to planarize the surface of said semiconductor substrate;

etching said first insulating film so as to allow the surface of said insulating film to further retreat;

burying a second insulating film in a manner to cover said first insulating film remaining in the bottom portion of said trench; and

removing that portion of said second insulating film which is deposited outside said trench.