Trench MIS device with reduced gate-to-drain capacitance

• US 6,882,000 B2
• Filed: 08/10/2001
• Issued: 04/19/2005
• Est. Priority Date: 08/10/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Terrill, Kyle, Chen, Kuo-In, Darwish, Mohamed N., Lui, Kam Hong, Giles, Frederick P.
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/927,320
• Publication Number:
  US 20030030092A1
• Time in Patent Office: 1,348 Days
• Field of Search: 257/301, 257/302, 257/303, 257/304, 438/242, 438/243, 438/244
• US Class Current: 257/307
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.

Claims

1. A metal-insulator-semiconductor device comprising:

a first drain region;

a body region disposed on a first surface of said first drain region;

a gate region extending through said body region and partially into said first drain region;

a source region disposed between a first portion of said body region and a first portion of said gate region;

a first insulative layer disposed between said source region and said first portion of said gate region and between said body region and a second portion of said gate region, wherein a thickness of said first insulative layer is in the range of approximately 100 to 1000 Å

; and

a second insulative layer disposed at least partially between a first portion of said first drain region and a third portion of said gate region and adjacent to said first insulative layer, wherein a thickness of said second insulative layer is in the range of approximate 0.1 to 0.3 μ

m, wherein said second insulative layer is not formed by oxidizing said first drain region and wherein said second insulative layer does not introduce substantial stress in said first drain region.

2. The metal-insulator-semiconductor device according to claim 1, wherein said gate region comprises polysilicon.

3. The metal-insulator-semiconductor device according to claim 1, further comprising a highly doped region formed in said first drain region adjacent said third portion of said gate region.

4. The metal-insulator-semiconductor device according to claim 1, wherein said first insulative layer comprises an oxide.

5. The metal-insulator-semiconductor device according to claim 1, wherein said second insulative layer is selected from the group consisting of phosphosilicate glass and borophosphosilicate glass.

6. A metal-insulator-semiconductor device comprising:

a first drain region;

a body region disposed on a first surface of said first drain region;

a gate region extending through said body region and partially into said first drain region;

a source region disposed between a first portion of said body region and a first portion of said gate region;

an oxide layer disposed between said source region and said first portion of said gate region, between a second portion of said body region and a second portion of said gate region and between a first portion of said first drain region and a third portion of said gate region, wherein a thickness of said oxide layer is in the range of approximate 100 to 1000 Å

; and

an insulative layer, selected from a group of material consisting of phosphosilicate glass and borophosphosilicate glass, disposed between a second portion of said first drain region and a fourth portion of said gate region and coupled to said oxide layer, wherein a thickness of said insulative layer is in the ranger of approximate 0.1 to 0.3 μ

m and wherein said insulative layer does not introduce substantial stress in said second portion of said first drain region.

7. The metal-insulator-semiconductor device according to claim 6, wherein said first drain region comprises a semiconductor of a first conductive type.

8. The metal-insulator-semiconductor device according to claim 6, wherein said body region comprises a semiconductor of a second conductive type.

9. The metal-insulator-semiconductor device according to claim 6, wherein said source region comprises a semiconductor of a first conductive type.

10. The metal-insulator-semiconductor device according to claim 6, further comprising a second drain region disposed on a second surface of said first drain region, wherein said second surface is opposite said first surface.

11. The metal-insulator-semiconductor device according to claim 10, wherein said second drain region comprises a semiconductor of a first conductive type semiconductor.

12. A metal-insulator-semiconductor device comprising:

a first drain region;

a body region disposed above said first drain region;

a gate region extending through said body region and partially into said first drain region;

a source region disposed between a first portion of said body region and a first portion of said gate region;

a silicon dioxide layer disposed between said source region and said first portion of said gate region, between a second portion of said body region and a second portion of said gate region and between a first portion of said first drain region and a third portion of said gate region, wherein a thickness of said silicon dioxide layer is in the rage of approximate 100 to 1000 Å

; and

an insulative layer, selected from a group of material consisting of phosphosilicate glass and borophosphosilicate glass, disposed between a second portion of said first drain region and a fourth portion of said gate region and coupled to said silicon dioxide layer, wherein a thickness of said insulative layer is in the range of approximately 0.1 to 0.3 μ

m and wherein said insulative layer does not introduce substantial stress in said first drain region.

13. The metal-insulator-semiconductor device according to claim 12, wherein said first drain region comprises a lightly n-doped semiconductor.

14. The metal-insulator-semiconductor device according to claim 13, wherein said body region comprises a p-doped semiconductor.

15. The metal-insulator-semiconductor device according to claim 14, wherein said source region comprises a heavily n-doped semiconductor.

16. The metal-insulator-semiconductor device according to claim 15, further comprising a second drain region disposed below said first drain region.

17. The metal-insulator-semiconductor device according to claim 16, wherein said second drain region comprises a heavily n-doped semiconductor.

18. The metal-insulator-semiconductor device according to claim 17, wherein said gate region comprises polysilicon.

19. The metal-insulator-semiconductor device according to claim 18, further comprising an n-doped semiconductor region disposed in said first drain region adjacent said fourth portion of said gate region.