Protection circuit for MOS components

• US 6,882,014 B2
• Filed: 08/16/2001
• Issued: 04/19/2005
• Est. Priority Date: 03/14/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tan, Chih-Ping
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US09/930,204
• Publication Number:
  US 20020130368A1
• Time in Patent Office: 1,342 Days
• Field of Search: 257/369, 257/355, 257/630, 257/356, 257/529, 257/528, 257/532, 324/750, 455/83, 363/126, 333/104, 330/310
• US Class Current: 257/369
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

A protection circuit for MOS components. In the protection circuit, a bypass PMOS transistor has a gate, a source and a substrate, all coupled to a first voltage node and a drain coupled to a gate of a MOS component. A bypass NMOS transistor has a gate, a source and a substrate, all coupled to a second voltage node and a drain coupled to the gate of the MOS component. When positive charges are accumulated on the gate of the MOS component due to an antenna effect, the bypass PMOS transistor dissipates the positive charges to the first voltage node. On the contrary, when negative charges are accumulated on the gate of the MOS component due to antenna effect, the bypass NMOS transistor dissipates the negative charges to the second voltage node.

Claims

1. A protection circuit for a MOS component comprising:

a bypass PMOS transistor, having a gate, a source and a substrate, all coupled to a first voltage node and a drain coupled to a gate of the MOS component;

a bypass NMOS transistor, having a gate, a source and a substrate, all coupled to a second voltage node and a drain coupled to the gate of the MOS component;

wherein when positive charges are accumulated on the gate of the MOS component due to antenna effect, the bypass PMOS transistor dissipates the positive charges to the first voltage node; and

when the negative charges are accumulated on the gate of the MOS component due to antenna effect, the bypass NMOS Transistor dissipates the negative charges to the second voltage node.